Patents by Inventor Summer Tseng

Summer Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7619435
    Abstract: A method and system for multi-point (e.g., double-point) GOI test that can efficiently judge failure modes by testing only two points. We can measure leakage currents at only two voltages, which are the cut points of mode A-B and B-C, instead of the whole ramped voltages to save time and cost with the same test effectiveness according to a specific embodiment. By correlating leakage current at extrinsic field to the breakdown voltage, we can also evaluate the intrinsic reliability even if the samples are not subjected to actual breakdown according to a specific embodiment.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: November 17, 2009
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Atman Zhao, Summer Tseng, W. T. Kary Chien, Excimer Gong
  • Patent number: 7573285
    Abstract: A method for testing a semiconductor wafer using an in-line process control, e.g., within one or more manufacturing processes in a wafer fabrication facility and/or test/sort operation. The method includes transferring a semiconductor wafer to a test station. The method includes applying an operating voltage on a gate of a test pattern on a semiconductor wafer using one or more probing devices. The method includes measuring a first leakage current associated with the operating voltage. If the measured first current is higher than a first predetermined amount, the device is an initial failure. If the measured first current is below the first predetermined amount, the device is subjected to a second voltage. The method includes applying the second voltage on the gate of the test pattern on the semiconductor wafer and measuring a second leakage current associated with the second voltage. If the second measured leakage current is higher than a second predetermined amount, the device is an extrinsic failure.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: August 11, 2009
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Atman Zhao, Summer Tseng, W. T. Kary Chien, Excimer Gong
  • Publication number: 20090085600
    Abstract: A method and system for multi-point (e.g., double-point) GOI test that can efficiently judge failure modes by testing only two points. We can measure leakage currents at only two voltages, which are the cut points of mode A-B and B-C, instead of the whole ramped voltages to save time and cost with the same test effectiveness according to a specific embodiment. By correlating leakage current at extrinsic field to the breakdown voltage, we can also evaluate the intrinsic reliability even if the samples are not subjected to actual breakdown according to a specific embodiment.
    Type: Application
    Filed: October 14, 2008
    Publication date: April 2, 2009
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Atman Zhao, Summer Tseng, W.T. Kary Chien, Excimer Gong
  • Publication number: 20090009209
    Abstract: A method for testing a semiconductor wafer using an in-line process control, e.g., within one or more manufacturing processes in a wafer fabrication facility and/or test/sort operation. The method includes transferring a semiconductor wafer to a test station. The method includes applying an operating voltage on a gate of a test pattern on a semiconductor wafer using one or more probing devices. The method includes measuring a first leakage current associated with the operating voltage. If the measured first current is higher than a first predetermined amount, the device is an initial failure. If the measured first current is below the first predetermined amount, the device is subjected to a second voltage. The method includes applying the second voltage on the gate of the test pattern on the semiconductor wafer and measuring a second leakage current associated with the second voltage. If the second measured leakage current is higher than a second predetermined amount, the device is an extrinsic failure.
    Type: Application
    Filed: June 6, 2008
    Publication date: January 8, 2009
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Atman Zhao, Summer Tseng, W.T. Kary Chien, Excimer Gong
  • Patent number: 7462497
    Abstract: A method and system for multi-point (e.g., double-point) GOI test that can efficiently judge failure modes by testing only two points. We can measure leakage currents at only two voltages, which are the cut points of mode A-B and B-C, instead of the whole ramped voltages to save time and cost with the same test effectiveness according to a specific embodiment. By correlating leakage current at extrinsic field to the breakdown voltage, we can also evaluate the intrinsic reliability even if the samples are not subjected to actual breakdown according to a specific embodiment.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: December 9, 2008
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Atman Zhao, Summer Tseng, W.T. Kary Chien, Excimer Gong
  • Patent number: 7396693
    Abstract: A method for testing a semiconductor wafer using an in-line process control, e.g., within one or more manufacturing processes in a wafer fabrication facility and/or test/sort operation. The method includes transferring a semiconductor wafer to a test station. The method includes applying an operating voltage on a gate of a test pattern on a semiconductor wafer using one or more probing devices. The method includes measuring a first leakage current associated with the operating voltage. If the measured first current is higher than a first predetermined amount, the device is an initial failure. If the measured first current is below the first predetermined amount, the device is subjected to a second voltage. The method includes applying the second voltage on the gate of the test pattern on the semiconductor wafer and measuring a second leakage current associated with the second voltage. If the second measured leakage current is higher than a second predetermined amount, the device is an extrinsic failure.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: July 8, 2008
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Atman Zhao, Summer Tseng, W. T. Kary Chien, Excimer Gong
  • Publication number: 20070059851
    Abstract: A method for testing a semiconductor wafer using an in-line process control, e.g., within one or more manufacturing processes in a wafer fabrication facility and/or test/sort operation. The method includes transferring a semiconductor wafer to a test station. The method includes applying an operating voltage on a gate of a test pattern on a semiconductor wafer using one or more probing devices. The method includes measuring a first leakage current associated with the operating voltage. If the measured first current is higher than a first predetermined amount, the device is an initial failure. If the measured first current is below the first predetermined amount, the device is subjected to a second voltage. The method includes applying the second voltage on the gate of the test pattern on the semiconductor wafer and measuring a second leakage current associated with the second voltage. If the second measured leakage current is higher than a second predetermined amount, the device is an extrinsic failure.
    Type: Application
    Filed: September 14, 2005
    Publication date: March 15, 2007
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Atman Zhao, Summer Tseng, W.T. Chien, Excimer Gong
  • Publication number: 20070059850
    Abstract: A method and system for multi-point (e.g., double-point) GOI test that can efficiently judge failure modes by testing only two points. We can measure leakage currents at only two voltages, which are the cut points of mode A-B and B-C, instead of the whole ramped voltages to save time and cost with the same test effectiveness according to a specific embodiment. By correlating leakage current at extrinsic field to the breakdown voltage, we can also evaluate the intrinsic reliability even if the samples are not subjected to actual breakdown according to a specific embodiment.
    Type: Application
    Filed: September 14, 2005
    Publication date: March 15, 2007
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Atman Zhao, Summer Tseng, W.T. Chien, Excimer Gong
  • Publication number: 20030108144
    Abstract: The present invention provides a clock control method for preventing the charge couple device from saturation. The charge couple device comprises a shift register, a last stage register and a pixel processing circuit. The clock control method for preventing the charge couple device from saturation is able to reduce the charge voltage sent to the last stage register from the shift register by controlling the signal transmission clock of the last stage register and the operating period of the reset clock of the pixel processing circuit, so as to prevent the saturation situation of the charge couple device from occurring. Moreover, better image quality is obtained by the proper clock control.
    Type: Application
    Filed: November 4, 2002
    Publication date: June 12, 2003
    Inventors: Summer Tseng, Shih-Huang Chen