Patents by Inventor Sumti Jairath

Sumti Jairath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210081769
    Abstract: The technology disclosed relates to allocating available physical compute units (PCUs) and/or physical memory units (PMUs) of a reconfigurable data processor to operation units of an operation unit graph for execution thereof. In particular, it relates to selecting, for evaluation, an intermediate stage compute processing time between lower and upper search bounds of a generic stage compute processing time, determining a pipeline number of the PCUs and/or the PMUs required to process the operation unit graph, and iteratively, initializing new lower and upper search bounds of the generic stage compute processing time and selecting, for evaluation in a next iteration, a new intermediate stage compute processing time taking into account whether the pipeline number of the PCUs and/or the PMUs produced for a prior intermediate stage compute processing time in a previous iteration is lower or higher than the available PCUs and/or PMUs.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Applicant: SambaNova Systems, Inc.
    Inventors: Zhuo CHEN, Sumti JAIRATH
  • Publication number: 20210081691
    Abstract: The technology disclosed relates to efficiently executing an operation unit graph on a reconfigurable data processor with a target architecture. In particular, it relates to reducing a number of physical compute units and/or physical memory units of the reconfigurable data processor required to execute the operation unit graph by receiving, from a user, architectural hints that are specific to the target architecture of the reconfigurable data processor, scanning the operation unit graph to detect instances of patterns of operation units specified by the architectural hints, and fusing operation units in the operation unit graph into a consolidated operation units block, thereby producing a fused operation unit graph.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Applicant: SambaNova Systems, Inc.
    Inventors: Zhuo CHEN, Sumti JAIRATH
  • Publication number: 20210055940
    Abstract: A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. Configurable units in the plurality of configurable units each include logic to execute a unit configuration load process, including receiving via the bus system, sub-files of a unit file particular to the configurable unit, and loading the received sub-files into the configuration store of the configurable unit. A configuration load controller connected to the bus system, including logic to execute an array configuration load process, including distributing a configuration file comprising unit files for a plurality of the configurable units in the array.
    Type: Application
    Filed: November 9, 2020
    Publication date: February 25, 2021
    Applicant: SambaNova Systems, Inc.
    Inventors: Manish K. Shah, Ram Sivaramakrishnan, Mark Luttrell, David B. Jackson, Raghu Prabhakar, Sumti Jairath, Gregory Frederick Grohoski, Pramod Nataraja
  • Publication number: 20210042259
    Abstract: The technology disclosed partitions a dataflow graph of a high-level program into memory allocations and execution fragments. The memory allocations represent creation of logical memory spaces in on-processor and/or off-processor memories for data required to implement the dataflow graph. The execution fragments represent operations on the data. The technology disclosed designates the memory allocations to virtual memory units and the execution fragments to virtual compute units. The technology disclosed partitions the execution fragments into memory fragments and compute fragments, and assigns the memory fragments to the virtual memory units and the compute fragments to the virtual compute units. The technology disclosed then allocates the virtual memory units to physical memory units and the virtual compute units to physical compute units.
    Type: Application
    Filed: August 8, 2019
    Publication date: February 11, 2021
    Applicant: SambaNova Systems, Inc.
    Inventors: David Alan KOEPLINGER, Raghu PRABHAKAR, Sumti JAIRATH
  • Publication number: 20210011770
    Abstract: A reconfigurable data processor comprises an array of configurable units configurable to allocate a plurality of sets of configurable units in the array to implement respective execution fragments of the data processing operation. Quiesce logic is coupled to configurable units in the array, configurable to respond to a quiesce control signal to quiesce the sets of configurable units in the array on quiesce boundaries of the respective execution fragments, and to forward quiesce ready signals for the respective execution fragments when the corresponding sets of processing units are ready. An array quiesce controller distributes the quiesce control signal to configurable units in the array, and receives quiesce ready signals for the respective execution fragments from the quiesce logic.
    Type: Application
    Filed: July 8, 2019
    Publication date: January 14, 2021
    Applicant: SambaNova Systems, Inc.
    Inventors: Raghu Prabhakar, Manish K. Shah, Pramod Nataraja, David Brian Jackson, Kin Hing Leung, Ram Sivaramakrishnan, Sumti Jairath, Gregory Frederick Grohoski
  • Patent number: 10831507
    Abstract: A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. Configurable units in the plurality of configurable units each include logic to execute a unit configuration load process, including receiving via the bus system, sub-files of a unit file particular to the configurable unit, and loading the received sub-files into the configuration store of the configurable unit. A configuration load controller connected to the bus system, including logic to execute an array configuration load process, including distributing a configuration file comprising unit files for a plurality of the configurable units in the array.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: November 10, 2020
    Assignee: SambaNova Systems, Inc.
    Inventors: Manish K. Shah, Ram Sivaramakrishnan, Mark Luttrell, David Brian Jackson, Raghu Prabhakar, Sumti Jairath, Gregory Frederick Grohoski, Pramod Nataraja
  • Publication number: 20200257643
    Abstract: A reconfigurable data processor comprises an array of configurable units and a bus system configurable to define virtual machines. The system can partition the array of configurable units into a plurality of sets of configurable units, and block communications via the bus system between configurable units within a particular set and configurable units outside the particular set. A memory access controller can be connected to the bus system, configurable to confine access to memory outside the array of configurable units originating from within the particular set to memory space allocated to the particular.
    Type: Application
    Filed: April 29, 2020
    Publication date: August 13, 2020
    Applicant: SambaNova Systems, Inc.
    Inventors: Gregory Frederick Grohoski, Sumti Jairath, Mark Luttrell, Raghu Prabhakar, Ram Sivaramakrishnan, Manish K. Shah
  • Publication number: 20200218683
    Abstract: A reconfigurable data processor comprises an array of configurable units and a bus system configurable to define virtual machines. The system can partition the array of configurable units into a plurality of sets of configurable units, and block communications via the bus system between configurable units within a particular set and configurable units outside the particular set. A memory access controller can be connected to the bus system, configurable to confine access to memory outside the array of configurable units originating from within the particular set to memory space allocated to the particular.
    Type: Application
    Filed: January 3, 2019
    Publication date: July 9, 2020
    Applicant: SambaNova Systems, Inc.
    Inventors: Gregory Frederick Grohoski, Sumti Jairath, Mark Luttrell, Raghu Prabhakar, Ram Sivaramakrishnan, Manish K. Shah
  • Patent number: 10698853
    Abstract: A reconfigurable data processor comprises an array of configurable units and a bus system configurable to define virtual machines. The system can partition the array of configurable units into a plurality of sets of configurable units, and block communications via the bus system between configurable units within a particular set and configurable units outside the particular set. A memory access controller can be connected to the bus system, configurable to confine access to memory outside the array of configurable units originating from within the particular set to memory space allocated to the particular.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: June 30, 2020
    Assignee: SambaNova Systems, Inc.
    Inventors: Gregory Frederick Grohoski, Sumti Jairath, Mark Luttrell, Raghu Prabhakar, Ram Sivaramakrishnan, Manish K Shah
  • Publication number: 20200159692
    Abstract: A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. Configurable units in the plurality of configurable units each include logic to execute a unit configuration load process, including receiving via the bus system, sub-files of a unit file particular to the configurable unit, and loading the received sub-files into the configuration store of the configurable unit. A configuration load controller connected to the bus system, including logic to execute an array configuration load process, including distributing a configuration file comprising unit files for a plurality of the configurable units in the array.
    Type: Application
    Filed: November 21, 2018
    Publication date: May 21, 2020
    Applicant: SambaNova Systems, Inc.
    Inventors: Manish K. Shah, Ram Sivaramakrishnan, Mark Luttrell, David Brian Jackson, Raghu Prabhakar, Sumti Jairath, Gregory Frederick Grohoski, Pramod Nataraja
  • Publication number: 20200159544
    Abstract: A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. Configurable units in the plurality of configurable units each include logic to execute a unit configuration load process, including receiving via the bus system, sub-files of a unit file particular to the configurable unit, and loading the received sub-files into the configuration store of the configurable unit. A configuration load controller connected to the bus system, including logic to execute an array configuration load process, including distributing a configuration file comprising unit files for a plurality of the configurable units in the array.
    Type: Application
    Filed: November 21, 2018
    Publication date: May 21, 2020
    Applicant: SambaNova Systems, Inc.
    Inventors: Manish K. Shah, Ram Sivaramakrishnan, Mark Luttrell, David Brian Jackson, Raghu Prabhakar, Sumti Jairath, Gregory Frederick Grohoski, Pramod Nataraja
  • Patent number: 10007629
    Abstract: A system is disclosed in which the system may include multiple bus switches, and multiple processors. Each processor may be coupled to each bus switch. Each processor may be configured to initiate a transfer of data to a given bus switch, and detect if a respective link to the given bus switch is inoperable. In response to detecting an inoperable link to a first bus switch, a given processor may be further configured to send a notification message to at least one other processor via at least a second bus switch and to remove routing information corresponding to the inoperable link from a first register. The at least one other processor may be configured to remove additional routing information corresponding to the inoperable link from a second register in response to receiving the notification message from the given processor.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: June 26, 2018
    Assignee: Oracle International Corporation
    Inventors: Thomas Wicki, David Smentek, Sumti Jairath, Kathirgamar Aingaran, Ali Vahidsafa, Paul Loewenstein
  • Patent number: 9836326
    Abstract: A method and system for allocating data streams that includes receiving, at an allocator, a data stream. The data stream includes a memory address and data associated with the memory address. The method also includes examining, by the allocator, the data stream to make a determination that the data stream is a soft allocating data stream, and then sending, from the allocator based on the determination, a plurality of write probes to a plurality of caches, wherein each write probe of the plurality of write probes includes at least part of the memory address. Additionally, the method includes receiving, at the allocator in response to a write probe of the plurality of write probes, a cache line present acknowledgement from a cache of the plurality of caches, and directing, by the allocator in response to the cache line present acknowledgement, the data of the data stream to the cache.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: December 5, 2017
    Assignee: Oracle International Corporation
    Inventors: David Richard Smentek, Kathirgamar Aingaran, Sumti Jairath, Manling Yang, Serena Wing Yee Leung, Paul N. Loewenstein
  • Patent number: 9836406
    Abstract: A method, system, and computer-readable medium for evicting cache lines that includes determining that a first cache line is to be evicted from a first Last Level Cache (LLC) partition of a partitioned LLC, and sending, based on the determination, a first notification to a second LLC partition of the partitioned LLC. The method may also include receiving, in response to the first notification, an available indication indicating that the second LLC partition is available as a designated victim cache partition; performing a selection of the second LLC partition as the designated victim cache partition; and evicting the first cache line to the second LLC partition based on the selection.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: December 5, 2017
    Assignee: Oracle International Corporation
    Inventors: Serena Wing Yee Leung, Ramaswamy Sivaramakrishnan, Sumti Jairath
  • Publication number: 20170177488
    Abstract: A method, system, and computer-readable medium for evicting cache lines that includes determining that a first cache line is to be evicted from a first Last Level Cache (LLC) partition of a partitioned LLC, and sending, based on the determination, a first notification to a second LLC partition of the partitioned LLC. The method may also include receiving, in response to the first notification, an available indication indicating that the second LLC partition is available as a designated victim cache partition; performing a selection of the second LLC partition as the designated victim cache partition; and evicting the first cache line to the second LLC partition based on the selection.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Inventors: Serena Wing Yee Leung, Ramaswamy Sivaramakrishnan, Sumti Jairath
  • Publication number: 20160210255
    Abstract: A system is disclosed in which the system may include multiple bus switches, and multiple processors. Each processor may be coupled to each bus switch. Each processor may be configured to initiate a transfer of data to a given bus switch, and detect if a respective link to the given bus switch is inoperable. In response to detecting an inoperable link to a first bus switch, a given processor may be further configured to send a notification message to at least one other processor via at least a second bus switch and to remove routing information corresponding to the inoperable link from a first register. The at least one other processor may be configured to remove additional routing information corresponding to the inoperable link from a second register in response to receiving the notification message from the given processor.
    Type: Application
    Filed: January 16, 2015
    Publication date: July 21, 2016
    Inventors: Thomas Wicki, David Smentek, Sumti Jairath, Kathirgamar Aingaran, Ali Vahidsafa, Paul Loewenstein
  • Patent number: 9372813
    Abstract: A system and method implementing revocable secure remote keys is disclosed. A plurality of indexed base secrets is stored in a register of a coprocessor of a local node coupled with a local memory. When it is determined that a selected base secret expired, the base secret stored in the register based on the base secret index is changed, thereby invalidating remote keys generated based on the expired base secret. A remote key with validation data and a base secret index is received from a node requesting access to the local memory. A validation base secret is obtained from the register based on the base secret index. The coprocessor performs hardware validation on the validation data based on the validation base secret. Hardware validation fails if the base secret associated with the base secret index has been changed in the register of the selected coprocessor.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 21, 2016
    Assignee: Oracle International Corporation
    Inventors: Sanjiv Kapil, Garret F. Swart, Aings Aingaran, William H. Bridge, Jr., Sumti Jairath, John G. Johnson
  • Patent number: 9158810
    Abstract: A method and apparatus for sending and receiving messages between nodes on a compute cluster is provided. Communication between nodes on a compute cluster, which do not share physical memory, is performed by passing messages over an I/O subsystem. Typically, each node includes a synchronization mechanism, a thread ready to receive connections, and other threads to process and reassemble messages. Frequently, a separate queue is maintained in memory for each node on the I/O subsystem sending messages to the receiving node. Such overhead increases latency and limits message throughput. Due to a specialized coprocessor running on each node, messages on an I/O subsystem are sent, received, authenticated, synchronized, and reassembled at a faster rate and with lower latency. Additionally, the memory structure used may reduce memory consumption by storing messages from multiple sources in the same memory structure, eliminating the need for per-source queues.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: October 13, 2015
    Assignee: Oracle International Corporation
    Inventors: Kathirgamar Aingaran, William H. Bridge, Jr., Garret F. Swart, Sumti Jairath, John G. Johnson
  • Publication number: 20150278092
    Abstract: A method and system for allocating data streams that includes receiving, at an allocator, a data stream. The data stream includes a memory address and data associated with the memory address. The method also includes examining, by the allocator, the data stream to make a determination that the data stream is a soft allocating data stream, and then sending, from the allocator based on the determination, a plurality of write probes to a plurality of caches, wherein each write probe of the plurality of write probes includes at least part of the memory address. Additionally, the method includes receiving, at the allocator in response to a write probe of the plurality of write probes, a cache line present acknowledgement from a cache of the plurality of caches, and directing, by the allocator in response to the cache line present acknowledgement, the data of the data stream to the cache.
    Type: Application
    Filed: March 31, 2015
    Publication date: October 1, 2015
    Inventors: David Richard Smentek, Kathirgamar Aingaran, Sumti Jairath, Manling Yang, Serena Wing Yee Leung, Paul N. Loewenstein
  • Patent number: 9026705
    Abstract: Techniques are disclosed relating to systems that allow sending and receiving of interrupts between processing elements. In various embodiments, a system includes an interrupt processing unit that in turn includes various indicators corresponding to processing elements. In some embodiments, the interrupt processing unit may be configured to receive an interrupt and determine whether a first processing element associated with the interrupt is available to receive interrupts. The system may initiate a corrective action if the first processing element is not available to receive interrupts. In some embodiments, the corrective action may include redirecting the interrupt to a second processing element. In some embodiments, the interrupt processing unit may include a dropped interrupt management register to store information corresponding to the second processing element.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: May 5, 2015
    Assignee: Oracle International Corporation
    Inventors: John R. Feehrer, Fred Han-Ching Tsai, Ali Vahidsafa, Sumti Jairath