Abstract: A discrete cosine transform chip includes circuits using neural network concepts that have parallel processing capability as well as conventional digital logic circuits. In particular, the discrete cosine transform chip includes a cosine term processing portion, a multiplier, an adder, a subtractor, and two groups of latches. The multiplier, the adder and the subtractor incorporated in the discrete cosine transform chip use unidirectional feed back neural network models.

Abstract: An integrated circuit for performing a square root operation uses adders made in accordance with neural network concepts. The integrated circuit includes an exponent part, a first mantissa part, a second mantissa part and a control part. The exponent part computes an exponent of the square root of an input operand; the first mantissa part preprocesses the mantissa of the input operand; the second mantissa part computes the square root of the output from the first mantissa part; and the control part controls interaction of input and output among various components of the integrated circuits. Because the adders used in integrated circuit are composed of neural network circuits having a short propagation time for carry bits, the integrated circuit can computer a square root fast and efficiently.

Abstract: A floating point multiplier circuit for multiplying two binary numbers includes a multiplier, a binary point processing device, a first network adder/subtracter, a second adder/subtracter, and a control device. In the floating point multiplier circuit, the circuit for operating the exponent and mantissa is designed using a parallel arrangement of PMOS and NMOS transistors. Faster operation is realized by transmitting in parallel a given input and a resulting output. Furthermore, the structure is much simpler than configurations using conventional logic gates thereby resulting in reduced chip area and efficient use of VLSI design methodologies.

Abstract: A sorting circuit for arranging data in sequence according to the magnitudes of the data values, uses the concept of a neural network. The sorting circuit is constructed of shift registers, magnitude comparators, binary counters, binary bit separators and registers.

Abstract: A rank filter is provided which can be used for improving an image signal degraded by noise, while at the same time maintaining edge information. The rank filter is implemented by using a neural network and obtains a high processing speed with a simple circuit arrangement, as compared to conventional rank filters, HPFs, LPFs and average filters. The rank filter using the concept of a neural network includes decoder devices, a comparison device and a counter.

Abstract: A digital multiplier for multiplying a binary N bit multiplicand by a binary N bit multiplier. The digital multiplier comprises a plurality of AND gates in which each digit of the mutliplicand is multiplied by each digit of the multiplier. The outputs of the AND gates represent partial products which are then arranged corresponding to each digit of the multiplier. The digital multiplier further comprises a plurality of 1's counters for receiving in parallel all partial products, except the least significant digit of the multiplier, and any carries propagated from an adjacent counter, and for counting the number of "1" in the resultant values. The 1's counters output the least significant bit as the final products, and propagate the remaining bits to the next 1's counter.

Abstract: An associative memory for storing an n-bit stored vector in m different states comprises n first amplifiers connected between n input terminals and n output terminals, and m second amplifiers to feedback to the input side the designated states of the stored vectors. Synapses of the storing unit store the above mentioned stored vectors in the a binary 1 or 0; synapses of the label units couple the respective intersections between the input and output lines of the second amplifiers; and synapses of the vector units couple the intersections between the output lines of the first amplifiers and the input lines of the second amplifiers. According to the present invention, the outputs of the amplifiers are stabilized, so that stabilized operations can be obtained.

Abstract: A binary adder is provided for adding-processing in a high speed parallel manner two N bit binary digits. The binary adder is implemented using neural network techniques and includes a number of amplifiers corresponding to the N bit output sum and a carry generation from the result of the adding process; an augend input-synapse group, an addend input-synapse group, a carry input-synapse group, a first bias-synapse group a second bias-synapse group an output feedback-synapse group and inverters. The binary adder is efficient and fast compared to conventional techniques.