Abstract: Provided is a memory device, including a plurality of memory banks. Each of the memory banks includes a memory array and a driver circuit. The driver circuit is coupled to the memory array, arranged to operably write data to the memory array according to write signals. The driver circuit includes a plurality of row driver circuits each coupled to a row of the memory cells. A global driver power circuit coupled to the row driver circuits in the plurality of memory banks to provide a global driver power. Each of the memory banks further includes a local driver power circuit coupled to respective row driver circuits in each of the memory banks to provide a local driver power. The local driver power circuit includes a first P-type MTCMOS coupled to a supply voltage and a control signal, controlled by the control signal to provide a local multi-threshold power signal to the respective row driver circuits.

Abstract: A memory core characteristic screening method includes the following steps. A command signal transmitting step includes configuring a processing module to transmit a command signal to a memory device. A first internal operating step includes configuring the memory device to operate a first operation to one of a word line, a bit line pair and a column line after a first strobe signal delay time according to a first command. A second internal operating step includes configuring the memory device to operate a second operation to another one of the word line, the bit line pair and the column line after a second strobe signal delay time according to a second command. A memory core characteristic screening step includes screening a memory core characteristic by shorting a timing between the first strobe signal delay time and the second strobe signal delay time.

Abstract: A semiconductor integrated circuit is provided, including: a first switch circuit; a logic circuit, coupled to the first switch circuit, a first floating diffusion point being defined between the first switch circuit and the logic circuit; a second switch circuit, coupled to the logic circuit, a second floating diffusion point being defined between the second switch circuit and the logic circuit; and a voltage holding circuit, coupled to the first floating diffusion point and the second floating diffusion point, and used to adjust the voltages of the floating diffusion points. The voltage holding circuit increases or decreases the voltage values of the first floating diffusion point and the second floating diffusion point. Thereby, the influence of long recovery time on the semiconductor integrated circuit is improved, and the stability is ensured.

Abstract: A memory interface circuitry includes a clock generator to convert the first clock signal into a second clock signal, a state machine to generate a test signal according to the second clock signal, a data pattern generator to generate a plurality of pre-defined data, a read register to sequentially output the plurality of pre-defined data, an I/O interface to capture a plurality of data from the plurality of pre-defined data according to a write strobe signal, a write register to receive and store the plurality of data from the I/O interface, and a comparator to compare the plurality of pre-defined data with the plurality of data to generate a test result. The test result is configured to verify an operation of the I/O interface.

Abstract: The present invention relates to a signal synchronization adjustment method and a signal synchronization adjustment circuit, for applying to data reading according to a reference clock signal between a memory controller and a dynamic random access memory in an electronic device. First, the memory controller triggers a command signal to the dynamic random access memory; then, the dynamic random access memory delays for a column selection signal latency time according to a first rising edge of the reference clock signal, and then triggers a column selection signal; after that, the dynamic random access memory delays for an internal data strobe signal latency time, and then triggers an internal data strobe signal; finally, the dynamic random access memory delays for an external data strobe signal latency time, and then triggers an external data strobe signal. The signal synchronization adjustment circuit is applied to the signal synchronization adjustment method.

Abstract: A semiconductor integrated circuit is provided, including: a first switch circuit; a logic circuit, coupled to the first switch circuit, a first floating diffusion point being defined between the first switch circuit and the logic circuit; a second switch circuit, coupled to the logic circuit, a second floating diffusion point being defined between the second switch circuit and the logic circuit; and a voltage holding circuit, coupled to the first floating diffusion point and the second floating diffusion point, and used to adjust the voltages of the floating diffusion points. The voltage holding circuit increases or decreases the voltage values of the first floating diffusion point and the second floating diffusion point. Thereby, the influence of long recovery time on the semiconductor integrated circuit is improved, and the stability is ensured.

Abstract: A memory interface circuitry includes a clock generator to convert the first clock signal into a second clock signal, a state machine to generate a test signal according to the second clock signal, a data pattern generator to generate a plurality of pre-defined data, a read register to sequentially output the plurality of pre-defined data, an I/O interface to capture a plurality of data from the plurality of pre-defined data according to a write strobe signal, a write register to receive and store the plurality of data from the I/O interface, and a comparator to compare the plurality of pre-defined data with the plurality of data to generate a test result. The test result is configured to verify an operation of the I/O interface.

Abstract: The present invention relates to a signal synchronization adjustment method and a signal synchronization adjustment circuit, for applying to data reading according to a reference clock signal between a memory controller and a dynamic random access memory in an electronic device. First, the memory controller triggers a command signal to the dynamic random access memory; then, the dynamic random access memory delays for a column selection signal latency time according to a first rising edge of the reference clock signal, and then triggers a column selection signal; after that, the dynamic random access memory delays for an internal data strobe signal latency time, and then triggers an internal data strobe signal; finally, the dynamic random access memory delays for an external data strobe signal latency time, and then triggers an external data strobe signal. The signal synchronization adjustment circuit is applied to the signal synchronization adjustment method.

Abstract: A memory core characteristic screening method includes the following steps. A command signal transmitting step includes configuring a processing module to transmit a command signal to a memory device. A first internal operating step includes configuring the memory device to operate a first operation to one of a word line, a bit line pair and a column line after a first strobe signal delay time according to a first command. A second internal operating step includes configuring the memory device to operate a second operation to another one of the word line, the bit line pair and the column line after a second strobe signal delay time according to a second command. A memory core characteristic screening step includes screening a memory core characteristic by shorting a timing between the first strobe signal delay time and the second strobe signal delay time.

Abstract: Provided is a memory device, including a plurality of memory banks. Each of the memory banks includes a memory array and a driver circuit. The driver circuit is coupled to the memory array, arranged to operably write data to the memory array according to write signals. The driver circuit includes a plurality of row driver circuits each coupled to a row of the memory cells. A global driver power circuit coupled to the row driver circuits in the plurality of memory banks to provide a global driver power. Each of the memory banks further includes a local driver power circuit coupled to respective row driver circuits in each of the memory banks to provide a local driver power. The local driver power circuit includes a first P-type MTCMOS coupled to a supply voltage and a control signal, controlled by the control signal to provide a local multi-threshold power signal to the respective row driver circuits.

Abstract: An internal latch circuit having a plurality of low initial value D flip-flops, a plurality of high initial value D flip-flops, an internal latch signal generating circuit and a NAND gate, and a method for generating latch signal thereof is provided. First, an input delay signal in response to a clock signal is generated. Then, a first internal input signal, a first reverse internal input signal, a second internal input signal, and a second reverse internal input signal are generated by using the low initial value D flip-flops and the high initial value D flip-flops, based on the internal data strobe signal and in response to the input delay signal, and are transmitted to the internal latch signal generating circuit. Then, the internal latch signal generating circuit outputs the first reverse pre-output signal and the second reverse pre-output signal. Finally, an internal latch signal is generated through a NAND gate.

Abstract: An integrated circuit memory device includes a test mode. Data is written to and read from the integrated circuit memory device in the test mode. The integrated circuit memory device includes a memory array that includes memory cells that store data. A test control circuit generates control signals that control the data read from the memory cells. A data output circuit outputs data read from the memory cells from the integrated circuit memory device in response to the test column address strobe signal. In particular, the test column address strobe signal includes a series of high to low and low to high transitions, wherein the data output circuit outputs data read from the memory cells in response to the series of high to low and low to high transitions.

Abstract: Current control systems and methods are provided for a plurality of integrated circuit devices that are commonly attached to a bus, including a plurality of signal lines. Each integrated circuit includes a plurality of output drivers, a respective one of which drives a respective one of the plurality of signal lines. Each integrated circuit includes a current setting circuit that sets an output current for each of the output drivers in the integrated circuit. A controlling circuit controls the current setting circuit in each integrated circuit, such that each current setting circuit simultaneously sets an output current for an output driver corresponding to a different one of the plurality of signal lines.