Abstract: A system of extending functionalities of a host device using a smart flash storage device comprises the host device having a host interface and configured to perform a specific function to generate a first set of data. The host device is coupled with a flash storage device. The flash storage device is configured to conform to a flash memory interface. A set of data generated by the host device is to be stored in flash memory storage of the flash storage device. A processor of the flash storage device is configured to run one or more user applications to process the set of data. The processor is to operate using power supplied by the host device.

Abstract: A system of extending functionalities of a host device using a smart flash storage device comprises the host device having a host interface and configured to perform a specific function to generate a first set of data. The host device is coupled with a flash storage device. The flash storage device is configured to conform to a flash memory interface. A set of data generated by the host device is to be stored in flash memory storage of the flash storage device. A processor of the flash storage device is configured to run one or more user applications to process the set of data. The processor is to operate using power supplied by the host device.

Abstract: According to some embodiments, a communication module 120 may be configured to transmit data packet traffic and a management module 110 may be configured to shape the data packet traffic transmitted by the communication module 120. The management module 110 may shape the data packet traffic by buffering data packets routed at different times to the communication module 120 based on at least one power management factor.

Abstract: Apparatus for joining a first conduit to a second conduit comprising a first coupler for attachment to an end of the first conduit, a second coupler for attachment to an end of the second conduit and for engagement to the first coupler, and a snap-fit fastener for fastening the first coupler to the second coupler. The snap-fit fastener is arranged in at least two portions to fit around the periphery of the first and second couplers when the first and second couplers are engaged. The apparatus enables relative movement between the first coupler and the second coupler.

Abstract: A system of extending functionalities of a host device using a smart flash storage device comprises the host device having a host interface and configured to perform a specific function to generate a first set of data. The host device is coupled with a flash storage device. The flash storage device is configured to conform to a flash memory interface. A set of data generated by the host device is to be stored in flash memory storage of the flash storage device. A processor of the flash storage device is configured to run one or more user applications to process the set of data. The processor is to operate using power supplied by the host device.

Abstract: According to some embodiments, a communication module 120 may be configured to transmit data packet traffic and a management module 110 may be configured to shape the data packet traffic transmitted by the communication module 120. The management module 110 may shape the data packet traffic by buffering data packets routed at different times to the communication module 120 based on at least one power management factor.

Abstract: Apparatus for joining a first conduit to a second conduit comprising a first coupler for attachment to an end of the first conduit, a second coupler for attachment to an end of the second conduit and for engagement to the first coupler, and a snap-fit fastener for fastening the first coupler to the second coupler. The snap-fit fastener is arranged in at least two portions to fit around the periphery of the first and second couplers when the first and second couplers are engaged. The apparatus enables relative movement between the first coupler and the second coupler.

Abstract: An intercooler configured for attachment to an automobile is disclosed. One embodiment of the invention includes an intercooler body having an inlet manifold on one end and an outlet manifold on the other end, and a decorative top plate on the top of the intercooler attached to the manifolds. The decorative top plate has two holes in it which are both keyed to resist rotation of an insert, a hollow bolt having a stepped formation under the bolt head such that the stepped formation is able to key in the hole cut in the plate, the bolt is inserted through the top of the plate and secured by a nut secured underneath it so that the head of the bolt lies flush against the plate and the stepped formation keys against the hole to prevent rotation. In addition, the bolt is hollow having a threaded passage passing through it to receive another bolt to secure the intercooler to a bracket in the automobile.

Abstract: A method and computer program product, within an optimizing compiler, for precise feedback data generation and updating. The method and computer program uses instrumentation and annotation of frequency values to allow feedback data to stay current during the multiple optimizations that the program code undergoes during compilation. Global propagation of known precise feedback values are used to replace approximate and unavailable values, and global verification of feedback data after optimization to detect discrepancies is employed. The method and computer program also provides improved instrumentation to anticipate cloning when code is cloned during ceratin compiler optimizations and handles inlined procedures. The result is compiled executables with improved SPECint benchmarks.

Abstract: A method for an allocation of stacked registers for Intel's Itanium® processor includes a three step process. Step I determines an intra-procedural stacked register usage by a program having a plurality of procedures. In step II, the disclosed method performs an inter-procedural analysis to assign quota of stacked register usage to every procedure. In step III, each procedure is allocated stacked register usage based on the quota assignments of step II.

Abstract: An intercooler configured for attachment to an automobile is disclosed. One embodiment of the invention includes an intercooler body having an inlet manifold on one end and an outlet manifold on the other end, and a decorative top plate on the top of the intercooler attached to the manifolds. The decorative top plate has two holes in it which are both keyed to resist rotation of an insert, a hollow bolt having a stepped formation under the bolt head such that the stepped formation is able to key in the hole cut in the plate, the bolt is inserted through the top of the plate and secured by a nut secured underneath it so that the head of the bolt lies flush against the plate and the stepped formation keys against the hole to prevent rotation. In addition, the bolt is hollow having a threaded passage passing through it to receive another bolt to secure the intercooler to a bracket in the automobile.

Abstract: A method for an allocation of stacked registers for Intel's Itanium® processor includes a three step process. Step I determines an intra-procedural stacked register usage by a program having a plurality of procedures. In step II, the disclosed method performs an inter-procedural analysis to assign quota of stacked register usage to every procedure. In step III, each procedure is allocated stacked register usage based on the quota assignments of step II.

Abstract: A method, system, and computer product uses a hashed static single assignment (SSA) form as a program representation and a medium for performing global scalar optimization. A compiler, after expressing the computer program in SSA form, can perform one or more static single assignment (SSA)-based, SSA-preserving global scalar optimization procedures on the SSA representation. Such a procedure modifies, (i.e., optimizes) the SSA representation of the program while preserving the utility of its embedded use-deprogram information for purposes of subsequent SSA-based, SSA-preserving global scalar optimizations. This saves the overhead expense of having to explicitly regenerate use-def program information for successive SSA-based, SSA-preserving global scalar optimizations.

Abstract: A system and method for an optimizer of a compilation suite for representing aliases and indirect memory operations in static single assignment (SSA) during compilation of a program having one or more basic blocks of source code. The optimizer converts all scalar variables of said program to SSA form, wherein said SSA form includes a plurality of variable versions, zero or more occurrences of a .chi. function, zero or more occurences of a .phi. function, and zero or more occurrences of a .mu. function. The .chi. function, .phi. function, and .mu. function are inserted for the variable versions. The optimizer also determines whether a variable version can be renamed to a zero version, and upon such a determination, the optimizer renames the variable version to a zero version.

Abstract: Partial redundancy elimination of a computer program is described that operates using a static single assignment (SSA) representation of a computer program. The SSA representation of the computer program is processed to eliminate partially redundant expressions in the computer program. This processing involves inserting .PHI. functions for expressions where different values of the expressions reach common points in the computer program. A result of each of the .PHI. functions is stored in a hypothetical variable h. The processing also involves a renaming step where SSA versions are assigned to hypothetical variables h in the computer program, a down safety step of determining whether each .PHI. function in the computer program is down safe, and a will be available step of determining whether each expression in the computer program will be available at each .PHI. function following eventual insertion of code into the computer program for purposes of partial redundancy elimination.

Abstract: A system and method for an optimizer of a compilation suite for representing aliases and indirect memory operations in static single assignment (SSA) during compilation of a program having one or more basic blocks of source code. The optimizer converts all scalar variables of said program to SSA form, wherein said SSA form includes a plurality of variable versions, zero or more occurrences of a .chi. function, zero or more occurences of a .phi. function, and zero or more occurrences of a .mu. function. The .chi. function, .phi. function, and .mu. function are inserted for the variable versions. The optimizer also determines whether a variable version can be renamed to a zero version, and upon such a determination, the optimizer renames the variable version to a zero version.

Abstract: A procedure which is a particular type of software pipelining is provided which increases the efficiency with which code is executed by reducing or eliminating stalls such as by filling delay slots. The process includes moving instructions in a loop from one loop iteration to another. The moving of instructions provides the scheduler with additional independent instructions in a given basic block so the scheduler has greater freedom to move instructions into unfilled delay slots. The procedure includes changing the entry point into the loop, thus effectively moving an instruction from near the top of the loop to near the bottom of the loop, while changing the iteration number of the moved instruction.