Patents by Inventor Sun Chu

Sun Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12053005
    Abstract: The present disclosure relates to a method for preparing a transglucosylated steviol glycoside using a crude enzyme liquid of a Lactobacillus mali strain.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: August 6, 2024
    Assignee: CJ CHEILJEDANG CORPORATION
    Inventors: Tae Joo Yang, Young Mi Lee, In Sung Kang, Sunghee Park, Young Su Lee, Sun Chu, Seong Bo Kim, Eun Jung Choi
  • Publication number: 20230276834
    Abstract: Provided is a sweetener composition including glucosylated rebaudioside A, glucosylated stevioside, and glucosylated rebaudioside C, a composition for preparing a sweetener, a method of preparing a sweetener using a steviol glycoside by-product, and a method of improving sweetness quality.
    Type: Application
    Filed: November 15, 2021
    Publication date: September 7, 2023
    Applicant: CJ CHEILJEDANG CORPORATION
    Inventors: Jungeun Kim, Sunghee Park, Sun Chu, Sung Bae Byun, Jae Yeong Ju
  • Publication number: 20230257796
    Abstract: Provided are a method of selecting dextransucrase having transglycosylation activity for glucose acceptors among enzymes, particularly dextransucrases, and a method of measuring activity thereof.
    Type: Application
    Filed: April 21, 2021
    Publication date: August 17, 2023
    Inventors: Jungeun KIM, Sun CHU, Sunghee PARK, Sung Bae BYUN, Jae Yeong JU
  • Publication number: 20220220523
    Abstract: The present disclosure relates to a composition for producing glucosylated steviol glycoside, the composition including glucosyltransferase including an amino acid sequence of SEQ ID NO: 1; and a method of producing glucosylated steviol glycoside using the same.
    Type: Application
    Filed: June 8, 2020
    Publication date: July 14, 2022
    Inventors: Jungeun KIM, Sunghee PARK, Tae Joo YANG, Sun CHU, Seong Bo KIM, Eun Jung CHOI
  • Publication number: 20220160009
    Abstract: The present disclosure relates to a sweetener composition comprising a transfructosylated steviol glycoside, and a method for improving the sweetness of a steviol glycoside, comprising converting a steviol glycoside into a transfructosylated steviol glycoside.
    Type: Application
    Filed: April 9, 2020
    Publication date: May 26, 2022
    Applicant: CJ CHEILJEDANG CORPORATION
    Inventors: Jung Eun Kim, Tae Joo Yang, Sunghee Park, In Sung Kang, Seong Bo Kim, Sun Chu
  • Patent number: 11332770
    Abstract: The present disclosure relates to a method for preparing a transfructosylated steviol glycoside using Arthrobacter-derived microorganisms, a culture thereof, a supernatant of the culture, an extract of the culture, and a lysate of the microorganisms.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: May 17, 2022
    Assignee: CJ CHEILJEDANG CORPORATION
    Inventors: Tae Joo Yang, In Sung Kang, Min Hoe Kim, Sunghee Park, Sun Chu, Seong Bo Kim, Young Mi Lee, Young Su Lee, Eun Jung Choi
  • Publication number: 20220132898
    Abstract: The present disclosure relates to a sweetener composition, comprising a transglycosylated Stevioside and a transglycosylated Rebaudioside A.
    Type: Application
    Filed: March 12, 2020
    Publication date: May 5, 2022
    Applicant: CJ CHEILJEDANG CORPORATION
    Inventors: Tae Joo Yang, Sun Chu, In Sung Kang, Min Hoe Kim, Sunghee Park
  • Publication number: 20220095656
    Abstract: The present invention relates to a sweetening material composition and a method for preparing the same. Specifically, the present invention relates to a sweetening material composition including transglycosylation steviol glycosides and a method for preparing the same. The sweetening material composition of the present invention includes transglycosylated stevia and saccharides, and the saccharides include 5 to 90 parts by weight of an oligosaccharide having a degree of polymerization (DP) of 3 or more with respect to 100 parts by weight.
    Type: Application
    Filed: May 22, 2020
    Publication date: March 31, 2022
    Applicant: CJ CHEILJEDANG CORPORATION
    Inventors: Jung Eun KIM, Sun CHU, Sung Hee PARK, Seong Bo KIM, Eun Jung CHOI
  • Publication number: 20200383364
    Abstract: The present disclosure relates to a method for preparing a transglucosylated steviol glycoside using a crude enzyme liquid of a Lactobacillus mali strain.
    Type: Application
    Filed: December 14, 2018
    Publication date: December 10, 2020
    Inventors: Tae Joo YANG, Young Mi LEE, In Sung KANG, Sunghee PARK, Young Su LEE, Sun CHU, Seong Bo KIM, Eun Jung CHOI
  • Publication number: 20200291443
    Abstract: The present disclosure relates to a method for preparing a transfructosylated steviol glycoside using Arthrobacter-derived microorganisms, a culture thereof, a supernatant of the culture, an extract of the culture, and a lysate of the microorganisms.
    Type: Application
    Filed: October 25, 2018
    Publication date: September 17, 2020
    Applicant: CJ Cheiljedang Corporation
    Inventors: Tae Joo Yang, In Sung Kang, Min Hoe Kim, Sunghee Park, Sun Chu, Seong Bo Kim, Young Mi Lee, Young Su Lee, Eun Jung Choi
  • Patent number: 8166377
    Abstract: The present invention discloses a configurable hierarchical comma-free Reed-Solomon decoding circuit and a method thereof. The design is based on an original hierarchical parallel architecture which not only completes a decoding process faster than conventional decoder, but also utilizes less hardware to perform various algorithms with less power consumed. The architecture of the present invention has higher decoding rate than the conventional systolic architecture by a cycle ratio of 22 to 94. Further, the present invention does not require the use of ROM to store 64 sets of codewords and uses logic gates less than one fourth of the logic gates than conventional systolic architecture. As a result, the circuit of the present invention occupies less area than the conventional architecture. The circuit of the present invention is also configurable for different applications, so it can always find an optimal compromise between speed and power consumption for various decoding requirements.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: April 24, 2012
    Assignee: National Chung Cheng University
    Inventors: Yuan-Sun Chu, Yi-Ren Chen, Chia-Ying Huang, Chi-Fang Li
  • Patent number: 8000352
    Abstract: A synchronizer for a communication device and an access point, which is installed inside the communication device and comprises a coefficient generator generating a set of coefficient code. A parallel-to-serial converter receives a set of input code from an access point, performs a parallel-to-serial conversion on the set of input code and outputs a result. A coefficient element array includes a plurality of coefficient elements interconnecting with each other. Each of the coefficient elements receives the set of input code from the parallel-to-serial converter and receives the set of coefficient code, and then performs a passive or active correlation operation on the set of input code and the set of coefficient code to output a correlation value to the access point for synchronizing signals of the communication device and the access point.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: August 16, 2011
    Assignee: National Chung Cheng University
    Inventors: Yuan-Sun Chu, Ting-Huan Li, Yi-Ren Chen, Chia-Ying Huang, Kuo-Hua Pu, Chi-Fang Li
  • Publication number: 20100146373
    Abstract: The present invention discloses a configurable hierarchical comma-free Reed-Solomon decoding circuit and a method thereof. The design is based on an original hierarchical parallel architecture which not only completes a decoding process faster than conventional decoder, but also utilizes less hardware to perform various algorithms with less power consumed. The architecture of the present invention has higher decoding rate than the conventional systolic architecture by a cycle ratio of 22 to 94. Further, the present invention does not require the use of ROM to store 64 sets of codewords and uses logic gates less than one fourth of the logic gates than conventional systolic architecture. As a result, the circuit of the present invention occupies less area than the conventional architecture. The circuit of the present invention is also configurable for different applications, so it can always find an optimal compromise between speed and power consumption for various decoding requirements.
    Type: Application
    Filed: April 15, 2009
    Publication date: June 10, 2010
    Inventors: Yuan-Sun CHU, Yi-Ren CHEN, Chia-Ying HUANG, Chi-Fang LI
  • Publication number: 20100142506
    Abstract: The present invention discloses a synchronizer for a communication device and an access point, which is installed inside the communication device and comprises a coefficient generator generating a set of coefficient code; a parallel-to-serial converter receiving a set of input code from an access point, performing a parallel-to-serial conversion on the set of input code and outputting a result; and a coefficient element array including a plurality of coefficient elements interconnecting with each other, wherein each of the coefficient elements receives the set of input code from the parallel-to-serial converter and receives the set of coefficient code, and then performs a passive or active correlation operation on the set of input code and the set of coefficient code to output a correlation value to the access point for synchronizing signals of the communication device and the access point.
    Type: Application
    Filed: April 7, 2009
    Publication date: June 10, 2010
    Inventors: Yuan-Sun Chu, Ting-Huan Li, Yi-Ren Chen, Chia-Ying Huang, Kuo-Hua Pu, Chi-Fang Li
  • Publication number: 20080225939
    Abstract: The present invention discloses a multifunctional video encoding circuit system capable of performing six types of operations: addition, subtraction, multiplication, multiply-accumulation, interpolation, and absolute difference summation. A partial product generation part, a partial product reduction part and an accumulation part of the circuit system are equipped with a virtual power suppression unit each for reducing the power consumption of the partial product generation part, the partial product reduction part and the accumulation part, so as to reduce the power consumption of the multifunctional video encoding circuit system.
    Type: Application
    Filed: March 15, 2007
    Publication date: September 18, 2008
    Inventors: JIUN-IN GUO, KUAN-HUNG CHEN, JINN-SHYAN WANG, YU-MIN CHEN, YUAN-SUN CHU
  • Publication number: 20080034115
    Abstract: An apparatus for handling hash collision of hash searching includes a hash table unit, a content addressable memory (CAM) and a multiplexer encoder. When the data are hashed to produce a hash index, and hash collision occurs, the data are stored into the CAM. When performing a hash search, the hash table unit and the CAM will be simultaneously looked up and the result will be found in only one period of time.
    Type: Application
    Filed: August 1, 2006
    Publication date: February 7, 2008
    Inventors: Yuan-Sun Chu, Jia-Huang Lin, Yi-Mao Hsiao
  • Patent number: 7051263
    Abstract: A Comma-Free Reed-Solomon decoding circuit based on systolic array architecture that applies to a cell search in a wideband code division multiple access system, and more particularly a decoding circuit that employs a systolic array in its circuit structure. The systolic array for the decoding circuit comprises an input pattern generator, a processing element array designed in the form of a systolic array and a boundary processing element array. Given the skewed-form output results required by the systolic array and generated by the input pattern generator, the processing element array makes a correlating comparison, and outputs the results of the correlating comparison to the boundary processing element, so as to acquire the decoding results required by the Comma-Free Reed-Solomon code. The results indicate the frame boundary and scrambling code groups of the cell search in a wideband code division multiple access system.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: May 23, 2006
    Assignee: Chung Shan Institute of Science and Technology
    Inventors: Chi-Fang Li, Wern-Ho Sheen, Yuan-Sun Chu, Jan-Shin Ho, Yuan-Tzu Ting
  • Patent number: 6944813
    Abstract: A weighted decoding method and circuits for Comma-Free Reed-Solomon codes that apply to a cell search in a wideband code division multiple access system. The invention also provides a weighted decoding method wherein the decoding result of the secondary synchronization code is used as a weight for received Comma-Free Reed-Solomon symbol data, and the weighted symbol data is input to the processing element array of the decoding circuit, so as to perform a weighted correlating comparison and thus enhance the accuracy of the decoding result. The weighted decoding method put forward by the invention may apply to a decoding architecture that is based on a systolic array and the decoding architecture that is based on a folding systolic array.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: September 13, 2005
    Assignee: Chung Shan Institute of Science and Technology
    Inventors: Chi-Fang Li, Wern-Ho Sheen, Yuan-Sun Chu, Jan-Shin Ho, Yuan-Tzu Ting
  • Patent number: 6928600
    Abstract: A kind of folding systolic array architecture for a CFRS decoding circuit that applies to a cell search in a wideband code division multiple access system. The invention involves using a systolic array for its decoding circuit and using a kind of folding technology to reduce the area of the systolic array. The systolic array for the decoding circuit comprises an input pattern generator, a processing element array designed in the form of a systolic array and a boundary processing element array. Given the skewed-form output results required by the systolic array and generated by the input pattern generator, the processing element array makes a set of correlating comparisons, and outputs the results of the correlating comparisons to the boundary processing elements, so as to acquire the decoding results required by the CFRS decoding. The results indicate the frame boundary and scrambling code groups of the cell search in a wideband code division multiple access system.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: August 9, 2005
    Assignee: Chung Shan Institute of Science and Technology
    Inventors: Chi-Fang Li, Wern-Ho Sheen, Yuan-Sun Chu, Jan-Shin Ho, Yuan-Tzu Ting
  • Publication number: 20050072586
    Abstract: The present invention of a axial sleeve for pneumatic tool axle is for reducing friction and abrasion between a tool axial sleeve and a tool axle, the axial sleeve mainly comprises an axial sleeve, a bushing ring and steel balls, which are disposed on an annular groove and are annularly arranged as well as in contact with each other, accordingly, the axial sleeve and the tool axle can last longer, transmission is more precise without vibration and high temperature, which can cause injury of hands.
    Type: Application
    Filed: October 6, 2003
    Publication date: April 7, 2005
    Inventor: Sun Chu