Patents by Inventor Sun Chul Kim
Sun Chul Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11862570Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.Type: GrantFiled: August 19, 2022Date of Patent: January 2, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Joo Kim, Sun Chul Kim, Min Keun Kwak, Hyun Ki Kim, Hyung Gil Baek, Yong Kwan Lee
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Publication number: 20230081723Abstract: A method of fabricating a semiconductor package includes disposing a preliminary semiconductor package on a stage, the preliminary semiconductor package including a substrate to which a pad part is attached, an interposer disposed on the substrate, and a semiconductor chip disposed between the substrate and the interposer. A bonding tool is disposed on the interposer. The bonding tool includes a first region and a second region outside of the first region. The second region of the bonding tool corresponds to the pad part. The interposer and the substrate are bonded to each other.Type: ApplicationFiled: May 31, 2022Publication date: March 16, 2023Inventors: JU HYUNG LEE, DONG UK KWON, SUN CHUL KIM, YONG HYUN KIM, MIN JAE LEE
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Patent number: 11562965Abstract: A semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a second substrate disposed on the first semiconductor chip, a second semiconductor chip disposed on the second substrate, and a mold layer disposed between the first substrate and the second substrate. The second substrate includes a recess formed at an edge, the mold layer fills the recess, and the recess protrudes concavely inward from the edge of the second substrate toward a center of the second substrate.Type: GrantFiled: December 28, 2020Date of Patent: January 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Chul Kim, Sang Soo Kim, Yong Kwan Lee, Hyun Ki Kim, Seok Geun Ahn, Jun Young Oh
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Patent number: 11545458Abstract: A semiconductor package includes a first semiconductor chip including a first body portion, a first bonding layer including a first bonding insulating layer, a first redistribution portion including first redistribution layers, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer including a second bonding insulating layer, a second redistribution portion including second redistribution layers, a second wiring insulating layer disposed between the second redistribution layers, and a second semiconductor chip disposed on the second redistribution portion. A lower surface of the first bonding insulating layer is bonded to an upper surface of the second bonding insulating layer, an upper surface of the first bonding insulating layer contacts the first body portion, a lower surface of the second bonding insulating layer contacts the second wiring insulating layer, and the first redistribution portion width is greater than the first semiconductor chip width.Type: GrantFiled: April 2, 2021Date of Patent: January 3, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Chul Kim, Tae Hun Kim, Ji Hwan Hwang
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Publication number: 20220392845Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.Type: ApplicationFiled: August 19, 2022Publication date: December 8, 2022Inventors: Jung Joo KIM, Sun Chul KIM, Min Keun KWAK, Hyun Ki KIM, Hyung Gil BAEK, Yong Kwan LEE
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Patent number: 11450614Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.Type: GrantFiled: September 28, 2020Date of Patent: September 20, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jung Joo Kim, Sun Chul Kim, Min Keun Kwak, Hyun Ki Kim, Hyung Gil Baek, Yong Kwan Lee
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Publication number: 20210366834Abstract: A semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a second substrate disposed on the first semiconductor chip, a second semiconductor chip disposed on the second substrate, and a mold layer disposed between the first substrate and the second substrate. The second substrate includes a recess formed at an edge, the mold layer fills the recess, and the recess protrudes concavely inward from the edge of the second substrate toward a center of the second substrate.Type: ApplicationFiled: December 28, 2020Publication date: November 25, 2021Inventors: Sun Chul Kim, Sang Soo Kim, Yong Kwan Lee, Hyun Ki Kim, Seok Geun Ahn, Jun Young Oh
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Publication number: 20210320067Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.Type: ApplicationFiled: September 28, 2020Publication date: October 14, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jung Joo KIM, Sun Chul KIM, Min Keun KWAK, Hyun Ki KIM, Hyung Gil BAEK, Yong Kwan LEE
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Publication number: 20210225796Abstract: A semiconductor package includes a first semiconductor chip including a first body portion, a first bonding layer including a first bonding insulating layer, a first redistribution portion including first redistribution layers, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer including a second bonding insulating layer, a second redistribution portion including second redistribution layers, a second wiring insulating layer disposed between the second redistribution layers, and a second semiconductor chip disposed on the second redistribution portion. A lower surface of the first bonding insulating layer is bonded to an upper surface of the second bonding insulating layer, an upper surface of the first bonding insulating layer contacts the first body portion, a lower surface of the second bonding insulating layer contacts the second wiring insulating layer, and the first redistribution portion width is greater than the first semiconductor chip width.Type: ApplicationFiled: April 2, 2021Publication date: July 22, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Chul KIM, Tae Hun KIM, Ji Hwan HWANG
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Patent number: 10971470Abstract: A semiconductor package includes a first semiconductor chip including a body portion, a first bonding layer disposed on a first surface of the body portion, and through vias passing through at least a portion of the body portion; and a first redistribution portion disposed in the first semiconductor chip to be connected to the first semiconductor chip through the first bonding layer, the first redistribution portion including first redistribution layers electrically connected to the first semiconductor chip, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer connected to the first bonding layer. The first bonding layer and the second bonding layer include first and metal pads disposed to correspond to each other and bonded to each other, respectively, and a first insulating layer and a second bonding insulating layer surrounding the first metal pads and the second metal pads, respectively.Type: GrantFiled: July 15, 2019Date of Patent: April 6, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Chul Kim, Tae Hun Kim, Ji Hwan Hwang
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Publication number: 20200135684Abstract: A semiconductor package includes a first semiconductor chip including a first bonding layer, on one surface, and a chip structure stacked on the first semiconductor chip and including a second bonding layer on a surface facing the first semiconductor chip and a plurality of second semiconductor chips. The plurality of second semiconductor chips includes a chip area and a scribe area outside of the chip area, respectively, the plurality of second semiconductor chips being connected to each other by the scribe area in the chip structure. The first and second bonding layers include first and second metal pads disposed to correspond to each other and bonded to each other, respectively and first and second bonding insulating layers surrounding the first and second metal pads, respectively.Type: ApplicationFiled: July 19, 2019Publication date: April 30, 2020Inventors: Sun Chul KIM, Tae Hun KIM, Ji Hwan HWANG
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Publication number: 20200135683Abstract: A semiconductor package includes a first semiconductor chip including a body portion, a first bonding layer disposed on a first surface of the body portion, and through vias passing through at least a portion of the body portion; and a first redistribution portion disposed in the first semiconductor chip to be connected to the first semiconductor chip through the first bonding layer, the first redistribution portion including first redistribution layers electrically connected to the first semiconductor chip, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer connected to the first bonding layer. The first bonding layer and the second bonding layer include first and metal pads disposed to correspond to each other and bonded to each other, respectively, and a first insulating layer and a second bonding insulating layer surrounding the first metal pads and the second metal pads, respectively.Type: ApplicationFiled: July 15, 2019Publication date: April 30, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun Chul Kim, Tae Hun Kim, Ji Hwan Hwang
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Publication number: 20090311917Abstract: An electric bulb socket is provided, which includes a socket body (100) (300) in the upper surface of which a recessed groove (101) (301) is formed, and a connection unit (200) (400) which is inserted into and fixed to the recessed groove (101) (301), and is provided with at least one entrance portion (201)(401), in which elastic pieces (230) (430) are arranged and fixed in inner spaces (203) (403) thereof and fixed conductive pieces (240) (440) respectively corresponding to the elastic pieces (230) (430) are arranged and fixed in the recessed groove (101) (301), so as to be integrally combined with the socket body (100) (300). Begun contents are thing about light bulb socket that insertion juncture of bare wire is simple. The electric bulb socket provides a stable electric power connection of bare wires, simplifies an assembly thereof and enables an electric appliance to be safely grounded.Type: ApplicationFiled: March 2, 2007Publication date: December 17, 2009Applicant: SHIN KWANG HI TECH CO., LTD.Inventor: Sun Chul Kim
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Patent number: 6694893Abstract: An art table having a top surface, two ends, and a lower tray. Each end has two legs. A brace is placed at each end supporting a plurality of holders, where drawing materials can be placed. Wheels are attached to two legs of one end. A paper dispenser is placed under the top surface and holds a roll of paper, so that paper can be fed over the top surface for drawing. The lower tray serves as a brace to provide extra support for the table and also serves as a holding place for extra papers and drawing materials.Type: GrantFiled: February 5, 2002Date of Patent: February 24, 2004Assignee: ABC School Supply, Inc.Inventors: Jose Alcala, Sofia Dumery, Sun Chul Kim, Kimberly Leonard, Andrew Schloss
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Publication number: 20020069792Abstract: An art table having a top surface, two ends, and a lower tray. Each end has two legs. A brace is placed at each end supporting a plurality of holders, where drawing materials can be placed. Wheels are attached to two legs of one end. A paper dispenser is placed under the top surface and holds a roll of paper, so that paper can be fed over the top surface for drawing. The lower tray serves as a brace to provide extra support for the table and also serves as a holding place for extra papers and drawing materials.Type: ApplicationFiled: February 5, 2002Publication date: June 13, 2002Applicant: ABC School Supply, Inc.Inventors: Jose Alcala, Sofia Dumery, Sun Chul Kim, Kimberly Leonard, Andrew Schloss
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Patent number: 6363865Abstract: An art table having a top surface, two ends, and a lower tray. Each end has two legs. A brace is placed at each end supporting a plurality of holders, where drawing materials can be placed. Wheels are attached to two legs of one end. A paper dispenser is placed under the top surface and holds a roll of paper, so that paper can be fed over the top surface for drawing. The lower tray serves as a brace to provide extra support for the table and also serves as a holding place for extra papers and drawing materials.Type: GrantFiled: January 7, 2000Date of Patent: April 2, 2002Assignee: ABC School Supply, Inc.Inventors: Jose Alcala, Sofia Dumery, Sun Chul Kim, Kimberly Leonard, Andrew Schloss
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Patent number: 6283544Abstract: The present specification discloses a children's furniture comprises a plurality of stalls, each stall defined by three walls and sharing a common wall with an adjacent stall. Each stall has a shelf, coat hooks, a seat and a storage area. Children can sit on the seat to put on and remove their shoes, and will store their shoes in the storage area under the seat. They can also hang their coats on the hooks provided here, and put their books and other belongings on the shelves.Type: GrantFiled: January 7, 2000Date of Patent: September 4, 2001Assignee: ABC School Supply, Inc.Inventors: Jose Alcala, Sofia Dumery, Sun Chul Kim, Kimberly Leonard, Andrew Schloss
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Patent number: 6171173Abstract: The present invention teaches a toy refrigerator with a body and a door that has an activity surface, which is either a metallic surface or a writing surface, such as a whiteboard. The body and the door is made either from plastic material or from wood. The activity surface is used as a space to teach children through use of additional play items such as magnetized alphabets or figures. The activity surface is alternatively used as writing or drawing or posting surface.Type: GrantFiled: January 7, 2000Date of Patent: January 9, 2001Assignee: ABC School Supply, Inc.Inventors: Jose Alcala, Sofia Dumery, Sun Chul Kim, Kimberly Leonard, Andrew Schloss
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Patent number: D436263Type: GrantFiled: February 4, 1999Date of Patent: January 16, 2001Assignee: ABC School Supply, Inc.Inventors: Jose Alcala, Sofia Dumery, Sun Chul Kim, Kimberly Leonard, Andrew Schloss
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Patent number: D437706Type: GrantFiled: October 8, 1999Date of Patent: February 20, 2001Assignee: ABC School Supply, Inc.Inventors: Jose Alcala, Sofia Dumery, Sun Chul Kim, Kimberly Leonard, Andrew Schloss