Patents by Inventor Sun Chul Kim

Sun Chul Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240147793
    Abstract: A display device includes: a substrate including a display area including a plurality of pixels and a non-display area around the display area; data lines extending from the display area; a multiplexer in the non-display area and connected to the data lines; a display driving circuit in the non-display area and on one side of the multiplexer; and fan-out lines connecting the multiplexer and the display driving circuit, wherein the fan-out lines include first fan-out lines connected to the multiplexer and second fan-out lines connected to the first fan-out lines and the display driving circuit, and the first fan-out lines and the second fan-out lines are on different layers.
    Type: Application
    Filed: October 3, 2023
    Publication date: May 2, 2024
    Inventors: Yang Hee KIM, Kwang Chul JUNG, Yong Jun JO, Sun Baek HONG
  • Patent number: 11967462
    Abstract: A capacitor component includes a body, including a dielectric layer and an internal electrode layer, and an external electrode disposed on the body and connected to the internal electrode layer. At least one hole is formed in the internal electrode layer, and a region, containing at least one selected from the group consisting of indium (In) and tin (Sn), is disposed in the hole. A method of manufacturing a capacitor component includes forming a dielectric green sheet, forming a conductive thin film, including a first conductive material and a second conductive material, on the dielectric green sheet, and sintering the conductive thin film to form an internal electrode layer. The internal electrode layer includes the first conductive material, and a region, including the second conductive material, is formed in the internal electrode layer.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: April 23, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yun Sung Kang, Su Yeon Lee, Won Jun Na, Byung Kun Kim, Yu Hong Oh, Sun Hwa Kim, Jae Eun Heo, Hoe Chul Jung
  • Publication number: 20240124062
    Abstract: A vehicle body structure includes: a roof side assembly connecting upper ends of pillars of a vehicle body along the forward/backward direction of the vehicle body, the roof side assembly constituting an A-pillar of the vehicle body; and an outer garnish coupled to the outside of the roof side assembly, wherein the roof side assembly includes: a pipe having a closed cross-section shape and elongated in the forward/backward direction of the vehicle body so as to form a closed section; an upper reinforcement member coupled to the upper side of the pipe and elongated in the forward/backward direction of the vehicle body; a lower reinforcement member coupled to the lower side of the pipe and elongated in the forward/backward direction of the vehicle body; and an inner reinforcement member coupled to the vehicle body inner side of the pipe and elongated in the forward/backward direction of the vehicle body.
    Type: Application
    Filed: April 13, 2023
    Publication date: April 18, 2024
    Applicants: Hyundai Motor Company, Kia Corporation, HYUNDAI MOBIS CO., LTD.
    Inventors: Do Hoi KIM, Sun Ho SONG, Jae Young LIM, Sea Cheoul SONG, Kang Chul LEE, Tae Ou PARK, Jae Sup BYUN, Jang Ho KIM
  • Publication number: 20240128502
    Abstract: An embodiment solid electrolyte includes a first compound and a second compound. The first compound is represented by a first chemical formula Li7-aPS6-a(X11-bX2b)a, wherein X1 and X2 are the same or different and each represents F, Cl, Br, or I, and wherein 0<a?2 and 0<b<1, and the second compound is represented by a second chemical formula Li7-cP1-2dMdS6-c-3d(X11-eX2e)c, wherein X1 and X2 are the same or different and each represents F, Cl, Br, or I, wherein M represents Ge, Si, Sn, or any combination thereof, and wherein 0<c?2, 0<d<0.5, and 0<e<1.
    Type: Application
    Filed: August 14, 2023
    Publication date: April 18, 2024
    Inventors: Sa Heum Kim, Yong Jun Jang, Yong Gu Kim, Sung Man Cho, Sun Ho Choi, Seong Hyeon Choi, Kyu Sung Park, Young Gyoon Ryu, Suk Gi Hong, Pil Sang Yun, Myeong Ju Ha, Hyun Beom Kim, Hwi Chul Yang
  • Publication number: 20240121543
    Abstract: An electronic device according to various embodiments of the present invention may comprise: a housing comprising a first surface facing in a first direction and a second surface facing in a second direction that is opposite to the first direction, the first surface comprising an at least partially transparent part and at least one opening formed adjacent to the at least partially transparent part; a camera positioned inside the housing, the camera comprising an image sensor facing in the first direction through the at least partially transparent part of the housing; and an acoustic component arranged between the first surface and the second surface, the acoustic component comprising a vibration plate configured to generate a sound such that the same moves in at least one direction selected from the first and second directions, a first passage formed in a third direction that is substantially perpendicular to the first direction such that the generated sound passes through the same, and a second passage forme
    Type: Application
    Filed: November 13, 2023
    Publication date: April 11, 2024
    Inventors: Young-Bae PARK, Byoung-Hee LEE, Jae-Hee YOU, Tae-Eon KIM, Han-Bom PARK, Sun-Young LEE, Byoung-Uk YOON, Kyung-Hee LEE, Ho-Chul HWANG
  • Publication number: 20240100469
    Abstract: The present disclosure relates to a pressure swing adsorption apparatus for hydrogen purification from decomposed ammonia gas and a hydrogen purification method using the same, and more particularly, the pressure swing adsorption apparatus of the present disclosure includes a plurality of adsorption towers including a pretreatment unit and a hydrogen purification unit wherein the adsorption towers of the pretreatment unit and the hydrogen purification unit are packed with different adsorbents, thereby achieving high purity hydrogen purification from mixed hydrogen gas produced after ammonia decomposition, making it easy to replace the adsorbent for ammonia removal, minimizing the likelihood that the lifetime of the adsorbent in the hydrogen purification unit is drastically reduced by a very small amount of ammonia, and actively responding to a large change in ammonia concentration in the raw material.
    Type: Application
    Filed: April 11, 2022
    Publication date: March 28, 2024
    Applicant: KOREA INSTITUTE OF ENERGY RESEARCH
    Inventors: Hyung-chul YOON, Sang-sup HAN, Hee-tae BEUM, Kanghee CHO, Sun Hyung KIM, Hyung Kuk JU
  • Publication number: 20240107852
    Abstract: A display device includes a substrate, pixel electrodes on the substrate, a bank in which opening areas partially exposing the pixel electrodes are defined, organic light emitting layers disposed on the pixel electrodes, a common electrode disposed on the organic light emitting layers and the bank, an encapsulation layer disposed on the common electrode, a touch electrode which is disposed on the encapsulation layer and does not overlap the opening areas in a thickness direction, a first adhesive member disposed on the touch electrode, a first light blocking layer which is disposed on the first adhesive member and does not overlap the opening areas in the thickness direction, color filters which are disposed on the first adhesive member and overlap the opening areas in the thickness direction, and a support layer which is disposed on the first light blocking layer and the color filters and includes a first organic material.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 28, 2024
    Inventors: So Young LEE, Sun Hwa KIM, Sung Chul KIM, Kwan Hee LEE, Jong Beom HONG
  • Patent number: 11943987
    Abstract: A color conversion substrate and a display device are provided. The color conversion substrate includes a base substrate, a first color filter and a second color filter disposed on a surface of the base substrate, a first partition layer disposed between the first color filter and the second color filter, a second partition layer disposed on the first partition layer, a first wavelength conversion pattern disposed on the first color filter and a second wavelength conversion pattern disposed on the second color filter, wherein the first partition layer includes a first lower surface disposed on the first color filter and a second lower surface disposed on the second color filter.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: March 26, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Gak Seok Lee, Byung Chul Kim, In Ok Kim, Jae Min Seong, In Seok Song, Keun Chan Oh, Ji Eun Jang, Chang Soon Jang, Sun Kyu Joo, Ha Lim Ji
  • Patent number: 11922225
    Abstract: Provided is a cluster node recommendation system. A method of controlling the cluster node recommendation system includes: inputting user selection information from a user, the user selection information including at least one of a cloud vendor, an Information Technology (IT) resource size, and a free resource size; checking resource requirements of a designated application; outputting a node configuration by inputting the input user selection information and the checked resource requirements of the application to an artificial intelligence module; verifying validity by arranging a container in which the application is executed, in the output node configuration; and providing a final node configuration in which validity verification is made, to the user.
    Type: Grant
    Filed: November 1, 2023
    Date of Patent: March 5, 2024
    Assignee: STRATO CO., LTD.
    Inventors: Hyeong-Doo Kim, Ho-Chul Lee, Sun-Kyu Park, Nam-Kyu Park, Yong-Min Kwon
  • Patent number: 11862570
    Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Joo Kim, Sun Chul Kim, Min Keun Kwak, Hyun Ki Kim, Hyung Gil Baek, Yong Kwan Lee
  • Publication number: 20230081723
    Abstract: A method of fabricating a semiconductor package includes disposing a preliminary semiconductor package on a stage, the preliminary semiconductor package including a substrate to which a pad part is attached, an interposer disposed on the substrate, and a semiconductor chip disposed between the substrate and the interposer. A bonding tool is disposed on the interposer. The bonding tool includes a first region and a second region outside of the first region. The second region of the bonding tool corresponds to the pad part. The interposer and the substrate are bonded to each other.
    Type: Application
    Filed: May 31, 2022
    Publication date: March 16, 2023
    Inventors: JU HYUNG LEE, DONG UK KWON, SUN CHUL KIM, YONG HYUN KIM, MIN JAE LEE
  • Patent number: 11562965
    Abstract: A semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a second substrate disposed on the first semiconductor chip, a second semiconductor chip disposed on the second substrate, and a mold layer disposed between the first substrate and the second substrate. The second substrate includes a recess formed at an edge, the mold layer fills the recess, and the recess protrudes concavely inward from the edge of the second substrate toward a center of the second substrate.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: January 24, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun Chul Kim, Sang Soo Kim, Yong Kwan Lee, Hyun Ki Kim, Seok Geun Ahn, Jun Young Oh
  • Patent number: 11545458
    Abstract: A semiconductor package includes a first semiconductor chip including a first body portion, a first bonding layer including a first bonding insulating layer, a first redistribution portion including first redistribution layers, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer including a second bonding insulating layer, a second redistribution portion including second redistribution layers, a second wiring insulating layer disposed between the second redistribution layers, and a second semiconductor chip disposed on the second redistribution portion. A lower surface of the first bonding insulating layer is bonded to an upper surface of the second bonding insulating layer, an upper surface of the first bonding insulating layer contacts the first body portion, a lower surface of the second bonding insulating layer contacts the second wiring insulating layer, and the first redistribution portion width is greater than the first semiconductor chip width.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: January 3, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun Chul Kim, Tae Hun Kim, Ji Hwan Hwang
  • Publication number: 20220392845
    Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.
    Type: Application
    Filed: August 19, 2022
    Publication date: December 8, 2022
    Inventors: Jung Joo KIM, Sun Chul KIM, Min Keun KWAK, Hyun Ki KIM, Hyung Gil BAEK, Yong Kwan LEE
  • Patent number: 11450614
    Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: September 20, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Joo Kim, Sun Chul Kim, Min Keun Kwak, Hyun Ki Kim, Hyung Gil Baek, Yong Kwan Lee
  • Publication number: 20210366834
    Abstract: A semiconductor package includes a first substrate, a first semiconductor chip disposed on the first substrate, a second substrate disposed on the first semiconductor chip, a second semiconductor chip disposed on the second substrate, and a mold layer disposed between the first substrate and the second substrate. The second substrate includes a recess formed at an edge, the mold layer fills the recess, and the recess protrudes concavely inward from the edge of the second substrate toward a center of the second substrate.
    Type: Application
    Filed: December 28, 2020
    Publication date: November 25, 2021
    Inventors: Sun Chul Kim, Sang Soo Kim, Yong Kwan Lee, Hyun Ki Kim, Seok Geun Ahn, Jun Young Oh
  • Publication number: 20210320067
    Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.
    Type: Application
    Filed: September 28, 2020
    Publication date: October 14, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung Joo KIM, Sun Chul KIM, Min Keun KWAK, Hyun Ki KIM, Hyung Gil BAEK, Yong Kwan LEE
  • Publication number: 20210225796
    Abstract: A semiconductor package includes a first semiconductor chip including a first body portion, a first bonding layer including a first bonding insulating layer, a first redistribution portion including first redistribution layers, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer including a second bonding insulating layer, a second redistribution portion including second redistribution layers, a second wiring insulating layer disposed between the second redistribution layers, and a second semiconductor chip disposed on the second redistribution portion. A lower surface of the first bonding insulating layer is bonded to an upper surface of the second bonding insulating layer, an upper surface of the first bonding insulating layer contacts the first body portion, a lower surface of the second bonding insulating layer contacts the second wiring insulating layer, and the first redistribution portion width is greater than the first semiconductor chip width.
    Type: Application
    Filed: April 2, 2021
    Publication date: July 22, 2021
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun Chul KIM, Tae Hun KIM, Ji Hwan HWANG
  • Patent number: 10971470
    Abstract: A semiconductor package includes a first semiconductor chip including a body portion, a first bonding layer disposed on a first surface of the body portion, and through vias passing through at least a portion of the body portion; and a first redistribution portion disposed in the first semiconductor chip to be connected to the first semiconductor chip through the first bonding layer, the first redistribution portion including first redistribution layers electrically connected to the first semiconductor chip, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer connected to the first bonding layer. The first bonding layer and the second bonding layer include first and metal pads disposed to correspond to each other and bonded to each other, respectively, and a first insulating layer and a second bonding insulating layer surrounding the first metal pads and the second metal pads, respectively.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun Chul Kim, Tae Hun Kim, Ji Hwan Hwang
  • Publication number: 20200135684
    Abstract: A semiconductor package includes a first semiconductor chip including a first bonding layer, on one surface, and a chip structure stacked on the first semiconductor chip and including a second bonding layer on a surface facing the first semiconductor chip and a plurality of second semiconductor chips. The plurality of second semiconductor chips includes a chip area and a scribe area outside of the chip area, respectively, the plurality of second semiconductor chips being connected to each other by the scribe area in the chip structure. The first and second bonding layers include first and second metal pads disposed to correspond to each other and bonded to each other, respectively and first and second bonding insulating layers surrounding the first and second metal pads, respectively.
    Type: Application
    Filed: July 19, 2019
    Publication date: April 30, 2020
    Inventors: Sun Chul KIM, Tae Hun KIM, Ji Hwan HWANG