Patents by Inventor Sun-ha Hwang
Sun-ha Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10381492Abstract: A MOS capacitor may include: an isolation layer formed in a substrate and defining an active region; a first electrode formed in the active region, and including an impurity region spaced from the isolation layer; and a second electrode formed over the substrate overlapping the impurity region, and including a gate having a plurality of gate patterns adjacent to each other with a gap therebetween.Type: GrantFiled: September 20, 2017Date of Patent: August 13, 2019Assignee: SK hynix Inc.Inventors: Sun-Ha Hwang, Pyong-Su Kwag, Sang-Uk Park, Kwang-Deok Kim, Ho-Ryeong Lee, Ju-Tae Ryu
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Publication number: 20180277688Abstract: A MOS capacitor may include: an isolation layer formed in a substrate and defining an active region; a first electrode formed in the active region, and including an impurity region spaced from the isolation layer; and a second electrode formed over the substrate overlapping the impurity region, and including a gate having a plurality of gate patterns adjacent to each other with a gap therebetween.Type: ApplicationFiled: September 20, 2017Publication date: September 27, 2018Inventors: Sun-Ha HWANG, Pyong-Su KWAG, Sang-Uk PARK, Kwang-Deok KIM, Ho-Ryeong LEE, Ju-Tae RYU
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Patent number: 9997556Abstract: An image sensor includes: a pixel array including a plurality of unit pixels that are arrayed in two dimensions, wherein each of the plurality of the unit pixels includes: a substrate that including a photoelectric conversion element; a recess pattern formed in the substrate to overlap with the photoelectric conversion element and correspond to a center of the photoelectric conversion element; a first gate suitable for filling at least the recess pattern; a second gate formed over the substrate to overlap with the photoelectric conversion element and to be adjacent to the first gate in a first diagonal direction; and a third gate formed over the substrate to overlap with the photoelectric conversion element and to be adjacent to the first gate in a second diagonal direction which intersects with the first diagonal direction.Type: GrantFiled: April 7, 2017Date of Patent: June 12, 2018Assignee: SK Hynix Inc.Inventor: Sun-Ha Hwang
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Publication number: 20180102392Abstract: An image sensor includes: a pixel array including a plurality of unit pixels that are arrayed in two dimensions, wherein each of the plurality of the unit pixels includes: a substrate that including a photoelectric conversion element; a recess pattern formed in the substrate to overlap with the photoelectric conversion element and correspond to a center of the photoelectric conversion element; a first gate suitable for filling at least the recess pattern; a second gate formed over the substrate to overlap with the photoelectric conversion element and to be adjacent to the first gate in a first diagonal direction; and a third gate formed over the substrate to overlap with the photoelectric conversion element and to be adjacent to the first gate in a second diagonal direction which intersects with the first diagonal direction.Type: ApplicationFiled: April 7, 2017Publication date: April 12, 2018Inventor: Sun-Ha HWANG
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Patent number: 9876042Abstract: The present disclosure provides an image sensor. An image sensor may include: a transfer gate formed over a first substrate, and having a through-hole; a column-shaped epitaxial body having a first portion filled in the through-hole and a second portion formed over the transfer gate; a photoelectric conversion element formed in the second portion of the epitaxial body; and a floating diffusion region formed in the first substrate, and contacting the first portion of the epitaxial body.Type: GrantFiled: September 15, 2015Date of Patent: January 23, 2018Assignee: SK Hynix Inc.Inventors: Kyung-Dong Yoo, Sun-Ha Hwang, Sung-Bo Hwang
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Publication number: 20160365375Abstract: The present disclosure provides an image sensor. An image sensor may include: a transfer gate formed over a first substrate, and having a through-hole; a column-shaped epitaxial body having a first portion filled in the through-hole and a second portion formed over the transfer gate; a photoelectric conversion element formed in the second portion of the epitaxial body; and a floating diffusion region formed in the first substrate, and contacting the first portion of the epitaxial body.Type: ApplicationFiled: September 15, 2015Publication date: December 15, 2016Inventors: Kyung-Dong YOO, Sun-Ha HWANG, Sung-Bo HWANG
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Patent number: 9196621Abstract: A semiconductor device includes a first and a second active regions having a first conductive type and a second conductive type, respectively, being arranged in a first direction; a gate extending in the first direction; a first and a second channel regions defined under the gate in the first and the active regions, respectively; a first low-concentration doped region, having the second conductive type, formed at sides of the gate in the first active region and a first high-concentration doped region, having the second conductive type, formed at sides of the first low-concentration doped region in the first active region; and a second low-concentration doped region, having the first conductive type, formed at sides of the gate in the second active region and a second high-concentration doped region, having the first conductive type, formed at sides of the second low-concentration doped region in the second active region.Type: GrantFiled: December 26, 2013Date of Patent: November 24, 2015Assignee: SK Hynix Inc.Inventor: Sun-Ha Hwang
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Publication number: 20150102415Abstract: A semiconductor device includes a first and a second active regions having a first conductive type and a second conductive type, respectively, being arranged in a first direction; a gate extending in the first direction; a first and a second channel regions defined under the gate in the first and the active regions, respectively; a first low-concentration doped region, having the second conductive type, formed at sides of the gate in the first active region and a first high-concentration doped region, having the second conductive type, formed at sides of the first low-concentration doped region in the first active region; and a second low-concentration doped region, having the first conductive type, formed at sides of the gate in the second active region and a second high-concentration doped region, having the first conductive type, formed at sides of the second low-concentration doped region in the second active region.Type: ApplicationFiled: December 26, 2013Publication date: April 16, 2015Applicant: SK hynix Inc.Inventor: Sun-Ha HWANG
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Patent number: 8497570Abstract: A wafer, a fabricating method of the same, and a semiconductor substrate are provided. The wafer includes a first substrate layer formed at a first surface, a second substrate layer formed at a second surface opposite to the first surface, the second substrate layer having a greater oxygen concentration than the first substrate layer, and an oxygen diffusion protecting layer formed between the first substrate layer and the second substrate layer, the oxygen diffusion protecting layer being located closer to the first surface than to the second surface.Type: GrantFiled: July 8, 2011Date of Patent: July 30, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Ha Hwang, Young-Soo Park, Sam-Jong Choi, Joon-Young Choi, Tae-Hyoung Koo
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Patent number: 8424195Abstract: An apparatus for manufacturing a semiconductor package includes an index rail transferring a lead frame in forward and backward directions, the lead frame having a first surface and a second surface that is opposite to the first surface, a loader portion connected to an end portion of the index rail and supplying the lead frame to the index rail, a frame driving portion connected to the opposite end portion of the end portion of the index rail and rotating the lead frame around a normal to the first surface, and a die attach portion attaching a semiconductor chip on the lead frame supplied to the index rail.Type: GrantFiled: February 26, 2009Date of Patent: April 23, 2013Assignee: STS Semiconductor & Telecommunications Co., Ltd.Inventor: Sun Ha Hwang
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Publication number: 20120056304Abstract: A wafer, a fabricating method of the same, and a semiconductor substrate are provided. The wafer includes a first substrate layer formed at a first surface, a second substrate layer formed at a second surface opposite to the first surface, the second substrate layer having a greater oxygen concentration than the first substrate layer, and an oxygen diffusion protecting layer formed between the first substrate layer and the second substrate layer, the oxygen diffusion protecting layer being located closer to the first surface than to the second surface.Type: ApplicationFiled: July 8, 2011Publication date: March 8, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sun-Ha Hwang, Young-Soo Park, Sam-Jong Choi, Joon-Young Choi, Tae-Hyoung Koo
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Patent number: 7934632Abstract: An apparatus for manufacturing a semiconductor package includes an index rail transferring a lead frame in forward and backward directions, the lead frame having a first surface and a second surface that is opposite to the first surface, a loader portion connected to an end portion of the index rail and supplying the lead frame to the index rail, a frame driving portion connected to the opposite end portion of the end portion of the index rail and rotating the lead frame around a normal to the first surface, and a wire bonding portion electrically connecting the lead frame and a semiconductor chip attached to the lead frame supplied to the index rail using a wire bond.Type: GrantFiled: February 26, 2009Date of Patent: May 3, 2011Assignee: STS Semiconductor & Telecommunications Co., Ltd.Inventor: Sun Ha Hwang
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Patent number: 7656008Abstract: Semiconductor devices are disclose that include a first doped region and a second doped region spaced apart from each other and defined within a same well of a semiconductor substrate. A gate insulating layer and a gate electrode are stacked on a channel region between the first and second doped regions. Spacers are on opposite sidewalls of gate electrode. A first surface metal silicide layer extends across a top surface of the first doped region adjacent to the spacer. A second surface metal silicide layer extends across a top surface of the second doped region adjacent to the spacer. At least one insulation layer extends across the semiconductor substrate including the first and second surface metal silicide layers. A first contact plug extends through the insulation layer and contacts the first surface metal silicide layer. A second contact plug extends through the insulation layer, the second surface metal silicide layer, and the second doped region into the well within the semiconductor substrate.Type: GrantFiled: January 2, 2008Date of Patent: February 2, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Sun-Ha Hwang
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Publication number: 20090269887Abstract: An apparatus for manufacturing a semiconductor package includes an index rail transferring a lead frame in forward and backward directions, the lead frame having a first surface and a second surface that is opposite to the first surface, a loader portion connected to an end portion of the index rail and supplying the lead frame to the index rail, a frame driving portion connected to the opposite end portion of the end portion of the index rail and rotating the lead frame around a normal to the first surface, and a die attach portion attaching a semiconductor chip on the lead frame supplied to the index rail.Type: ApplicationFiled: February 26, 2009Publication date: October 29, 2009Applicant: STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD.Inventor: Sun Ha HWANG
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Publication number: 20090269889Abstract: An apparatus for manufacturing a semiconductor package includes an index rail transferring a lead frame in forward and backward directions, the lead frame having a first surface and a second surface that is opposite to the first surface, a loader portion connected to an end portion of the index rail and supplying the lead frame to the index rail, a frame driving portion connected to the opposite end portion of the end portion of the index rail and rotating the lead frame around a normal to the first surface, and a wire bonding portion electrically connecting the lead frame and a semiconductor chip attached to the lead frame supplied to the index rail using a wire bond.Type: ApplicationFiled: February 26, 2009Publication date: October 29, 2009Applicant: STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD.Inventor: Sun Ha HWANG
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Publication number: 20080169515Abstract: Semiconductor devices are disclose that include a first doped region and a second doped region spaced apart from each other and defined within a same well of a semiconductor substrate. A gate insulating layer and a gate electrode are stacked on a channel region between the first and second doped regions. Spacers are on opposite sidewalls of gate electrode. A first surface metal silicide layer extends across a top surface of the first doped region adjacent to the spacer. A second surface metal silicide layer extends across a top surface of the second doped region adjacent to the spacer. At least one insulation layer extends across the semiconductor substrate including the first and second surface metal silicide layers. A first contact plug extends through the insulation layer and contacts the first surface metal silicide layer. A second contact plug extends through the insulation layer, the second surface metal silicide layer, and the second doped region into the well within the semiconductor substrate.Type: ApplicationFiled: January 2, 2008Publication date: July 17, 2008Inventor: Sun-Ha Hwang
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Patent number: 7074683Abstract: A semiconductor device comprises a device isolation layer disposed in a portion of a substrate of first conductivity type. An outline of the device isolation layer defines an active region of the substrate. An impurity diffused region of second conductivity type may be formed in a portion of the active region; and a silicide layer may be formed to cover the impurity diffused region of second conductivity type. The device isolation layer may include a recess formed therein to expose a portion of the substrate of first conductivity type adjacent to the impurity diffused region of second conductivity type. The silicide layer that is formed to cover the impurity diffused layer of second conductivity type may extend over and against the exposed region of the substrate of first conductivity type that was exposed by the recess of the device isolation layer.Type: GrantFiled: March 8, 2004Date of Patent: July 11, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Ha Hwang, Young-Ok Kim, Cha-Dong Yeo
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Publication number: 20040180502Abstract: A semiconductor device comprises a device isolation layer disposed in a portion of a substrate of first conductivity type. An outline of the device isolation layer defines an active region of the substrate. An impurity diffused region of second conductivity type may be formed in a portion of the active region; and a silicide layer may be formed to cover the impurity diffused region of second conductivity type. The device isolation layer may include a recess formed therein to expose a portion of the substrate of first conductivity type adjacent to the impurity diffused region of second conductivity type. The silicide layer that is formed to cover the impurity diffused layer of second conductivity type may extend over and against the exposed region of the substrate of first conductivity type that was exposed by the recess of the device isolation layer.Type: ApplicationFiled: March 8, 2004Publication date: September 16, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-Ha Hwang, Young-Ok Kim, Cha-Dong Yeo
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Patent number: 6730971Abstract: A semiconductor device comprises a device isolation layer disposed in a portion of a substrate of first conductivity type. An outline of the device isolation layer defines an active region of the substrate. An impurity diffused region of second conductivity type may be formed in a portion of the active region; and a silicide layer may be formed to cover the impurity diffused region of second conductivity type. The device isolation layer may include a recess formed therein to expose a portion of the substrate of first conductivity type adjacent to the impurity diffused region of second conductivity type. The silicide layer that is formed to cover the impurity diffused layer of second conductivity type may extend over and against the exposed region of the substrate of first conductivity type that was exposed by the recess of the device isolation layer.Type: GrantFiled: November 6, 2002Date of Patent: May 4, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Ha Hwang, Young-Ok Kim, Cha-Dong Yeo
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Publication number: 20030111708Abstract: A semiconductor device comprises a device isolation layer disposed in a portion of a substrate of first conductivity type. An outline of the device isolation layer defines an active region of the substrate. An impurity diffused region of second conductivity type may be formed in a portion of the active region; and a silicide layer may be formed to cover the impurity diffused region of second conductivity type. The device isolation layer may include a recess formed therein to expose a portion of the substrate of first conductivity type adjacent to the impurity diffused region of second conductivity type. The silicide layer that is formed to cover the impurity diffused layer of second conductivity type may extend over and against the exposed region of the substrate of first conductivity type that was exposed by the recess of the device isolation layer.Type: ApplicationFiled: November 6, 2002Publication date: June 19, 2003Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-Ha Hwang, Young-Ok Kim, Cha-Dong Yeo