Abstract: Embodiments relate to a data conversion unit including a color analysis portion configured to determine based on R (red), G (green) and B (blue) data signals among the R, G, B data signals and W (white) data signal for an input image whether or not the input image includes a pure color component; and a brightness adjustment portion configured to adjust brightness of the W data signal according to a hue of the pure color component included in the input image.

Abstract: A bump structure may include a body portion spaced apart from a pad disposed on a substrate and a first extension extending from a side of the body portion onto the pad. A second extension extends from another side of the body portion.

Abstract: An electrical interconnection can be provided using a bump stack including at least two solder bumps which are stacked on one another and at least one intermediate layer interposed between the at least stacked two solder bumps.

Abstract: A system on chip (SoC) including a configurable image processing pipeline is provided. The SoC includes a bus; a first image processing module configured to be connected to the bus and to process image data; a first image processing stage configured to transmit either first image data or second image data received from the bus to at least one of the bus and the first image processing module through a first bypass path in response to first control signals; and a second image processing stage configured to transmit either third image data received from the first image processing module or fourth image data received from the bus to the bus through one of a second bypass path and a second scaler path in response to second control signals.

Abstract: A multi-chip package may include first and second semiconductor chips, an insulating layer structure and a plug structure. The first semiconductor chip may include a first bonding pad. The second semiconductor chip may be positioned over the first semiconductor chip. The second semiconductor chip may include a second bonding pad. The insulating layer structure may cover side surfaces and at least portions of upper surfaces of the semiconductor chips. The plug structure may be formed in the insulating layer structure by a plating process. The plug structure may be arranged spaced apart from side surfaces of the semiconductor chips to electrically connect the first bonding pad and the second bonding pad with each other. A third semiconductor chip having a third bonding pad may be positioned over the second semiconductor chip. Thus, a process for forming a micro bump between the plugs need not be performed.

Abstract: A camera module includes an image sensor configured to convert an optical signal received through a lens into an electrical signal and generate full-size image data, an image signal processing unit configured to calibrate and output the full-size image data, a first memory unit configured to periodically receive and store the full-size image data from the image signal processing unit, a scaling unit configured to scale down the full-size image data received from the first memory unit and periodically output scaled-down image data to a display device, and an encoder configured to receive the full-size image data stored in the first memory unit, convert it into a compressed file in a predetermined format, and output the compressed file upon opening of a shutter.

Abstract: Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Abstract: A bump structure may include a body portion spaced apart from a pad disposed on a substrate and a first extension extending from a side of the body portion onto the pad. A second extension extends from another side of the body portion.

Abstract: A method may include providing a substrate including a chip pad, forming on the substrate a solder stack including at least two solder layers which are stacked and at least one intermediate layer interposed between the at least two solder layers. The solder stack can be reflowed to form a bump stack that is electrically connected to the chip pad. The bump stack may include at least two solder bumps which are stacked and the at least one intermediate layer interposed between the at least two solder bumps. Related structures are also disclosed.

Abstract: A multi-chip package may include first and second semiconductor chips, an insulating layer structure and a plug structure. The first semiconductor chip may include a first bonding pad. The second semiconductor chip may be positioned over the first semiconductor chip. The second semiconductor chip may include a second bonding pad. The insulating layer structure may cover side surfaces and at least portions of upper surfaces of the semiconductor chips. The plug structure may be formed in the insulating layer structure by a plating process. The plug structure may be arranged spaced apart from side surfaces of the semiconductor chips to electrically connect the first bonding pad and the second bonding pad with each other. A third semiconductor chip having a third bonding pad may be positioned over the second semiconductor chip. Thus, a process for forming a micro bump between the plugs need not be performed.

Abstract: A semiconductor package includes a semiconductor chip having a plurality of contact pads on a surface thereof, a plurality of main bumps on the contact pads, respectively. Each of the plurality of main bumps includes a first pillar layer on one of the contact pads and a first solder layer on the first pillar layer, and the first solder layer includes an upper portion having an overhang portion.

Abstract: In a method of forming a conductive pattern structure of a semiconductor device, a first insulating interlayer is formed on a substrate. A first wiring is formed to pass through the first insulating interlayer. An etch stop layer and a second insulating interlayer are sequentially formed on the first insulating interlayer. A second wiring is formed to pass through the second insulating interlayer and the etch stop layer. A dummy pattern is formed to pass through the second insulating layer and the etch stop layer at the same time as forming the second wiring. The second wiring is electrically connected to the first wiring. The dummy pattern is electrically isolated from the second wiring.

Abstract: Methods of forming connection bumps for semiconductor devices in which rewiring patterns are formed. The method includes preparing a semiconductor substrate on which a pad is partially exposed through a passivation film, forming a seed layer on the pad and passivation film, forming a photoresist pattern including an opening pattern comprising a first opening that exposes a portion of the seed layer on the pad and a second opening that exposes a portion of the seed layer on the passivation film and is separated from the first opening, performing a first electroplating to form filler layers in the opening patterns, performing a second electroplating to form a solder layer on the filler layers, removing the photoresist pattern and performing a reflow process to form a collapsed solder layer that electrically connects the filler layers to each other and a solder bump on the filler layer formed in the second opening.

Abstract: A semiconductor chip includes stress-relief to mitigate the effects of differences in coefficients of thermal expansion (CTE) between a printed circuit board (PCB) and a semiconductor chip and a flip-chip package including the semiconductor chip. The semiconductor chip includes a stress-relief buffer coupling a bump and a semiconductor chip pad.

Abstract: Provided are an optical cavity enhanced turbidimeter and a turbidity measure method. After casting a pulse beam or a beam having a steep intensity gradient into an optical cavity, the turbidity of the inside region of the optical cavity can be calculated using an attenuation rate of an output beam from the optical cavity.

Abstract: In a method of forming a conductive pattern structure of a semiconductor device, a first insulating interlayer is formed on a substrate. A first wiring is formed to pass through the first insulating interlayer. An etch stop layer and a second insulating interlayer are sequentially formed on the first insulating interlayer. A second wiring is formed to pass through the second insulating interlayer and the etch stop layer. A dummy pattern is formed to pass through the second insulating layer and the etch stop layer at the same time as forming the second wiring. The second wiring is electrically connected to the first wiring. The dummy pattern is electrically isolated from the second wiring.

Abstract: A system on chip (Soc) includes a system bus, a plurality of sub-systems, an image processing logic block, an image memory interface and an image processing memory block. The sub-systems are respectively connected to the system bus. The image processing logic block is connected to the system bus. The image processing logic block performs an image processing. The image processing logic block is included in a first power domain. The image memory interface is connected to the system bus and the image processing logic block. The image processing memory block is connected to the image memory interface. The image processing memory block is used for the image processing. The image memory interface and the image processing memory block are included in a second power domain different from the first power domain.

Abstract: Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Abstract: The present invention provides an apparatus for detecting metal concentration from an area including compounding a solution that includes a metal dissolved by a solvent, and a reagent combined with metal ions dissolved in the solution and referring a difference of absorption rates between a compound of the solvent and reagent and a compound of the solution and reagent.

Abstract: A camera module includes an image sensor configured to convert an optical signal received through a lens into an electrical signal and generate full-size image data, an image signal processing unit configured to calibrate and output the full-size image data, a first memory unit configured to periodically receive and store the full-size image data from the image signal processing unit, a scaling unit configured to scale down the full-size image data received from the first memory unit and periodically output scaled-down image data to a display device, and an encoder configured to receive the full-size image data stored in the first memory unit, convert it into a compressed file in a predetermined format, and output the compressed file upon opening of a shutter.