Patents by Inventor Sunhom Paak
Sunhom Paak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9576613Abstract: A semiconductor device may include a semiconductor substrate; a test circuit array region; a pad region on the semiconductor substrate and at at least a first side of the test circuit array region and outside of the test circuit array region, transistors arranged in the test circuit array region in a first direction and a second direction perpendicular to the first direction, source lines spaced apart from each other in the second direction, each of the source lines extending in the first direction and electrically connected to corresponding source electrodes of the transistors, and drain lines spaced apart from each other in the second direction, each of the drain lines extending in the first direction and electrically connected to drain electrodes of the transistors.Type: GrantFiled: December 16, 2014Date of Patent: February 21, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Steve Sunhom Paak, Kangwook Park, Heonjong Shin, Sunil Yu, Jongmil Youn, Hyungsoon Jang
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Publication number: 20150255123Abstract: A semiconductor device may include a semiconductor substrate; a test circuit array region; a pad region on the semiconductor substrate and at at least a first side of the test circuit array region and outside of the test circuit array region, transistors arranged in the test circuit array region in a first direction and a second direction perpendicular to the first direction, source lines spaced apart from each other in the second direction, each of the source lines extending in the first direction and electrically connected to corresponding source electrodes of the transistors, and drain lines spaced apart from each other in the second direction, each of the drain lines extending in the first direction and electrically connected to drain electrodes of the transistors.Type: ApplicationFiled: December 16, 2014Publication date: September 10, 2015Inventors: STEVE SUNHOM PAAK, KANGWOOK PARK, HEONJONG SHIN, SUNIL YU, JONGMIL YOUN, HYUNGSOON JANG
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Publication number: 20140060609Abstract: Apparatuses and assembly methods are provided for a monolithic solar cell panel assembly. The assembly comprises an array of solar cells having front electrical contacts and back electrical contacts, wherein a first set of the solar cells in the array are aligned to be electrically connected in series through a back circuit sheet having an array of back metal contacts connected to corresponding back electrical contacts on the first set of solar cells, and through a front circuit sheet having an array of front metal contacts connected to corresponding front electrical contacts on the first set of solar cells. Electrical connections may be made in a lamination step, in which an encapsulant polymer flows into gaps and an interconnect material connects the circuits to form the monolithic solar cell panel assembly.Type: ApplicationFiled: October 8, 2012Publication date: March 6, 2014Applicant: APPLIED MATERIALS, INC.Inventors: PRABHAT KUMAR, Sunhom Paak, James M. Gee
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Patent number: 8564023Abstract: At least one MOS parameter of a MOS fuse is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse is programmed by applying a programming signal to the fuse terminals so that programming current flows through the fuse link. The fuse resistance is measured to provide a measured fuse resistance associated with a first logic value. A MOS parameter of the programmed MOS fuse is measured to provide a measured MOS parameter value. The measured MOS parameter value is compared to the reference MOS parameter value to determine a second logic value of the MOS fuse, and a bit value is output based on the comparison.Type: GrantFiled: March 6, 2008Date of Patent: October 22, 2013Assignee: Xilinx, Inc.Inventors: Hsung Jai Im, Sunhom Paak, Boon Yong Ang
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Publication number: 20120100666Abstract: Embodiments of the invention generally provide a solar cell formation process that includes the formation of metal contacts over heavily doped regions that are formed in a desired pattern on a surface of a substrate. Embodiments of the invention also provide an inspection system and supporting hardware that is used to reliably position a similarly shaped, or patterned, metal contact structure on the patterned heavily doped regions to allow an Ohmic contact to be made. The metal contact structure, such as fingers and busbars, are formed on the heavily doped regions so that a high quality electrical connection can be formed between these two regions.Type: ApplicationFiled: October 26, 2011Publication date: April 26, 2012Applicant: APPLIED MATERIALS ITALIA S.R.L.Inventors: James M. Gee, Asaf Schlezinger, Marco Galiazzo, Andrea Baccini, Timothy W. Weidman, Sunhom Paak, Hongbin Fang, Zhenhua Zhang
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Publication number: 20110272024Abstract: Embodiments of the invention include a solar cell and methods of forming a solar cell. Specifically, the methods may be used to form a passivation/anti-reflection layer having combined functional and optical gradient properties on a solar cell substrate. The methods may include flowing a first process gas mixture into a process volume within a processing chamber generating plasma in the processing chamber at a power density of greater than 0.65 W/cm2 depositing a silicon nitride-containing interface sub-layer on a solar cell substrate in the process volume, flowing a second process gas mixture into the process volume, and depositing a silicon nitride-containing bulk sub-layer on the silicon nitride-containing interface sub-layer.Type: ApplicationFiled: March 30, 2011Publication date: November 10, 2011Applicant: APPLIED MATERIALS, INC.Inventors: Dongwon Choi, Michael P. Stewart, Li Xu, Hemant P. Mungekar, Sunhom Paak, Kenneth MacWilliams
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Publication number: 20110272008Abstract: Embodiments of the invention generally provide methods for forming a multilayer rear surface passivation layer on a solar cell substrate. The method includes forming a silicon oxide sub-layer having a net charge density of less than or equal to 2.1×1011 Coulombs/cm2 on a rear surface of a p-type doped region formed in a substrate comprising semiconductor material, the rear surface opposite a light receiving surface of the substrate and forming a silicon nitride sub-layer on the silicon oxide sub-layer. Embodiments of the invention also include a solar cell device that may be manufactured according methods disclosed herein.Type: ApplicationFiled: May 5, 2011Publication date: November 10, 2011Applicant: APPLIED MATERIALS, INC.Inventors: Hemant P. Mungekar, Mukul Agrawal, Michael P. Stewart, Timothy W. Weidman, Rohit Mishra, Sunhom Paak
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Patent number: 7923811Abstract: An electronic fuse (“E-fuse”) cell is formed on a semiconductor substrate. The E-fuse cell has a fuse element with a fuse link extending from a first fuse terminal across a thick dielectric structure to a second fuse terminal. The first and second fuse terminals are separated from the semiconductor substrate by a thin dielectric layer.Type: GrantFiled: March 6, 2008Date of Patent: April 12, 2011Assignee: Xilinx, Inc.Inventors: Hsung Jai Im, Sunhom Paak, Boon Yong Ang
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Patent number: 7839693Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.Type: GrantFiled: January 7, 2010Date of Patent: November 23, 2010Assignee: Xilinix, Inc.Inventors: Sunhom Paak, Boon Y. Ang, Hsung J. Im, Daniel Gitlin
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Patent number: 7834659Abstract: E-fuses in an E-fuse memory array are programmed by applying a first programming pulse to a plurality of E-fuses to program the plurality of E-fuses to a first state; and then applying a second programming pulse to at least a selected E-fuse in the plurality of E-fuses to program the selected E-fuse to a second state.Type: GrantFiled: March 5, 2008Date of Patent: November 16, 2010Assignee: Xilinx, Inc.Inventors: Hsung Jai Im, Sunhom Paak, Boon Yong Ang
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Patent number: 7760538Abstract: A non-volatile static random access memory (“SRAM”) cell using variable resistance random access memory (“RAM”) cells is described. A memory tri-cell includes an SRAM cell with a first charge node and a second charge node. A first variable resistance random access memory cell is coupled between the first charge node and a supply voltage bus. A second variable resistance random access memory cell is coupled between the first charge node and a ground bus. A first control gate is coupled between the supply voltage bus and the first variable resistance random access memory cell. A second control gate is coupled between the ground bus and the second variable resistance random access memory cell.Type: GrantFiled: March 4, 2008Date of Patent: July 20, 2010Assignee: Xilinx, Inc.Inventor: Sunhom Paak
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Patent number: 7746696Abstract: A memory has first and second storage cells, each with a floating node, that store complementary data values. Interlaced inverters quickly sense a voltage difference between the storage cells and provide a data value output when the memory is read. Each floating node includes a tunneling gate of a tunneling transistor, a gate of a bitline transistor, and a plate of a coupling capacitor.Type: GrantFiled: March 4, 2008Date of Patent: June 29, 2010Assignee: XILINX, Inc.Inventor: Sunhom Paak
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Patent number: 7724600Abstract: An integrated circuit includes an electronic fuse (“E-fuse”) cell having a fuse link and an E-fuse programming current generator. The fuse link has a width (FLw) and a thickness (FLT) and is fabricated from a layer of link material. An E-fuse programming current generator includes a reference link array having a plurality of reference links. Each of the reference links has the fuse link width and the fuse link thickness, and is fabricated from the layer of link material.Type: GrantFiled: March 5, 2008Date of Patent: May 25, 2010Assignee: XILINX, Inc.Inventors: Hsung Jai Im, Sunhom Paak, Boon Yong Ang
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Patent number: 7710813Abstract: An electronic fuse memory array has an array core with a plurality of selectable unit cells. A unit cell has a fuse and a cell transistor (M12). A programming current path goes through the fuse and the cell transistor to a word line ground and a read current path also goes through the fuse and the cell transistor to the word line ground.Type: GrantFiled: March 5, 2008Date of Patent: May 4, 2010Assignee: Xilinx, Inc.Inventors: Hsung Jai Im, Sunhom Paak, Raymond C. Pang, Boon Yong Ang, Serhii Tumakha
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Patent number: 7688639Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.Type: GrantFiled: October 12, 2007Date of Patent: March 30, 2010Assignee: Xilinx, Inc.Inventors: Sunhom Paak, Boon Yong Ang, Hsung Jai Im, Daniel Gitlin
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Patent number: 7598749Abstract: An integrated circuit with an efuse having an efuse link includes a damage detection structure disposed in relation to the efuse so as to detect damage in the IC resulting from programming the efuse. Damage sensing circuitry is optionally included on the IC. Embodiments are used in evaluation wafers to determine proper efuse fabrication and programming parameters, and in production ICs to identify efuse programming damage that might create a latent defect.Type: GrantFiled: June 8, 2006Date of Patent: October 6, 2009Assignee: XILINX, Inc.Inventors: Boon Yong Ang, Sunhom Paak, Hsung Jai Im, Kwansuhk Oh, Raymond C. Pang
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Publication number: 20090224323Abstract: At least one MOS parameter of a MOS fuse is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse is programmed by applying a programming signal to the fuse terminals so that programming current flows through the fuse link. The fuse resistance is measured to provide a measured fuse resistance associated with a first logic value. A MOS parameter of the programmed MOS fuse is measured to provide a measured MOS parameter value. The measured MOS parameter value is compared to the reference MOS parameter value to determine a second logic value of the MOS fuse, and a bit value is output based on the comparison.Type: ApplicationFiled: March 6, 2008Publication date: September 10, 2009Applicant: XILINX, INC.Inventors: Hsung Jai Im, Sunhom Paak, Boon Yong Ang
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Patent number: 7567449Abstract: A memory cell with a logic bit has a first one-time-programmable (“OTP”) memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP memory element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element.Type: GrantFiled: October 27, 2006Date of Patent: July 28, 2009Assignee: XILINX, Inc.Inventors: Sunhom Paak, Hsung Jai Im, Boon Yong Ang
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Patent number: 7501879Abstract: An eFuse sensing circuit replaces the inverters used to provide the “read” output state of a conventional eFuse circuit. The sensing circuit includes a comparator with one input coupled to the eFuse circuitry, and a second input coupled to a reference voltage generator circuit. The reference voltage generator circuit includes an internal resistor. Transistors of the sense circuit are provided to mimic the transistors of the eFuse circuit, so that variations of transistors due to process, voltage and temperature will be substantially the same. The resistor of the sense circuit is then effectively compared with the resistance of the eFuse by the comparator irrespective of temperature and process variations.Type: GrantFiled: March 13, 2007Date of Patent: March 10, 2009Assignee: Xilinx, Inc.Inventors: Kwansuhk Oh, Raymond C. Pang, Hsung Jai Im, Sunhom Paak
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Publication number: 20080101146Abstract: A memory cell with a logic bit has a first one-time-programmable (“OTP”) memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP memory element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element.Type: ApplicationFiled: October 27, 2006Publication date: May 1, 2008Applicant: Xilinx, Inc.Inventors: Sunhom Paak, Hsung Jai Im, Boon Yong Ang