Patents by Inventor Sun-Hung Chen

Sun-Hung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260143707
    Abstract: The invention discloses a semiconductor device including a substrate, a stacked structure, a trench, a channel structure, and a barrier layer. The stacked structure is disposed on the substrate, wherein the stacked structure includes a first metal layer, at least one stacked layer and a second metal layer from bottom to top. The trench is disposed in the stacked structure. The channel structure is disposed in the trench, wherein the channel structure fills up the trench. The barrier layer is disposed in the second metal layer, wherein the trench penetrates through the barrier layer. Therefore, the barrier layer can effectively prevent the diffusion of metal ions in the second metal layer from polluting the channel structure in the trench, and the structural reliability and performance of the semiconductor device can be improved.
    Type: Application
    Filed: January 6, 2026
    Publication date: May 21, 2026
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: YU CHUN LIN, Sun-Hung Chen, Anqi Liu
  • Patent number: 12543314
    Abstract: The invention discloses a semiconductor device including a substrate, a stacked structure, a trench, a channel structure, and a barrier layer. The stacked structure is disposed on the substrate, wherein the stacked structure includes a first metal layer, at least one stacked layer and a second metal layer from bottom to top. The trench is disposed in the stacked structure. The channel structure is disposed in the trench, wherein the channel structure fills up the trench. The barrier layer is disposed in the second metal layer, wherein the trench penetrates through the barrier layer. Therefore, the barrier layer can effectively prevent the diffusion of metal ions in the second metal layer from polluting the channel structure in the trench, and the structural reliability and performance of the semiconductor device can be improved.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: February 3, 2026
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu Chun Lin, Sun-Hung Chen, Anqi Liu
  • Patent number: 12213303
    Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, and which includes a substrate, bit lines, bit line contacts, a gate structure, a first oxidized interface layer, and a second oxidized interface layer. The bit lines are disposed on the substrate, and the bit line contacts are disposed below the bit lines. The gate structure is disposed on the substrate, wherein each bit line and the gate structure respectively include a semiconductor layer, a conductive layer, and a covering layer stacked from bottom to top. The first oxidized interface layer is disposed between each bit line contact and the semiconductor layer of each bit line. The second oxidized interface layer is disposed within the semiconductor layer of the gate structure, wherein a topmost surface of the first oxidized interface layer is higher than a topmost surface of the second oxidized interface layer.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: January 28, 2025
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yukihiro Nagai, Lu-Yung Lin, Chia-Wei Wu, Tsun-Min Cheng, Yu Chun Lin, Zheng Guo Zhang, Sun-Hung Chen, Wu Xiang Li, Hsiao-Han Lin
  • Publication number: 20240224518
    Abstract: The invention discloses a semiconductor device including a substrate, a stacked structure, a trench, a channel structure, and a barrier layer. The stacked structure is disposed on the substrate, wherein the stacked structure includes a first metal layer, at least one stacked layer and a second metal layer from bottom to top. The trench is disposed in the stacked structure. The channel structure is disposed in the trench, wherein the channel structure fills up the trench. The barrier layer is disposed in the second metal layer, wherein the trench penetrates through the barrier layer. Therefore, the barrier layer can effectively prevent the diffusion of metal ions in the second metal layer from polluting the channel structure in the trench, and the structural reliability and performance of the semiconductor device can be improved.
    Type: Application
    Filed: February 14, 2023
    Publication date: July 4, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: YU CHUN LIN, Sun-Hung Chen, Anqi Liu
  • Publication number: 20230284436
    Abstract: The present disclosure provides a semiconductor device and a fabricating method thereof, and which includes a substrate, bit lines, bit line contacts, a gate structure, a first oxidized interface layer, and a second oxidized interface layer. The bit lines are disposed on the substrate, and the bit line contacts are disposed below the bit lines. The gate structure is disposed on the substrate, wherein each bit line and the gate structure respectively include a semiconductor layer, a conductive layer, and a covering layer stacked from bottom to top. The first oxidized interface layer is disposed between each bit line contact and the semiconductor layer of each bit line. The second oxidized interface layer is disposed within the semiconductor layer of the gate structure, wherein a topmost surface of the first oxidized interface layer is higher than a topmost surface of the second oxidized interface layer.
    Type: Application
    Filed: April 21, 2022
    Publication date: September 7, 2023
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yukihiro Nagai, Lu-Yung Lin, Chia-Wei Wu, Tsun-Min Cheng, Yu Chun Lin, Zheng Guo Zhang, Sun-Hung Chen, Wu Xiang Li, Hsiao-Han Lin
  • Patent number: 11069559
    Abstract: A semiconductor structure and method for forming such a structure are disclosed by the present invention. In the method, before a first trench in a pre-processed substrate is filled with any filling material, an auxiliary layer is formed over an inner surface of the first trench. Afterward, a first filling dielectric is formed and an etch back process is performed so that a top surface of the first filling dielectric is higher than that of the pre-processed substrate, and a second filling dielectric is then formed and subject to a second planarization process.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: July 20, 2021
    Assignee: NEXCHIP SEMICONDUCTOR CORPORATION
    Inventors: Sun-Hung Chen, Tsun-Min Cheng, Jui-Min Lee, Wei Xiang, Renwei Zhu