Patents by Inventor Sun-Hye Lee

Sun-Hye Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220256152
    Abstract: Provided is a method of decoding motion information characterized in that information for determining motion-related information includes spatial information and time information, wherein the spatial information indicates a direction of spatial prediction candidates used for sub-units from among spatial prediction candidates located on a left side and an upper side of a current prediction unit, and the time information indicates a reference prediction unit of a previous picture used for prediction of the current prediction unit. Further, an encoding apparatus or a decoding apparatus capable of performing the above described encoding or decoding method may be provided.
    Type: Application
    Filed: May 2, 2022
    Publication date: August 11, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun-il LEE, Jung-hye MIN, Na-rae CHOI
  • Publication number: 20210328039
    Abstract: A semiconductor device includes first and second active patterns each extending in a first direction and are spaced apart from each other in a second direction that is perpendicular to the first direction. A field insulating layer is disposed between the first active pattern and the second active pattern. A first gate structure is disposed on the first active pattern and extends in the second direction. An interlayer insulating layer is disposed between the first gate structure and the field insulating layer. The interlayer insulating layer includes a first part disposed below the first gate structure. A spacer is disposed between the first gate structure and the first part of the interlayer insulating layer.
    Type: Application
    Filed: December 4, 2020
    Publication date: October 21, 2021
    Inventors: Sun Hye LEE, Sung Soo KIM, Ik Soo KIM, Woong Sik NAM, Dong Hyun ROH
  • Patent number: 9400281
    Abstract: Provided are compounds for inhibiting Snail-p53 binding and therapeutic agents for cancer including the compounds as an effective component. The Snail-p53 binding inhibitors induce expression of p53 in K-Ras mutant cell lines, thereby enabling effective treatment or prevention of K-Ras mutant cancer, such as, pancreatic cancer, lung cancer, cholangioma, and colon cancer, of which diagnosis or treatment is not easy.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: July 26, 2016
    Assignees: PUSAN NATIONAL UNIVERSITY INDUSTRY-UNIVERSITY COOPERATION FOUNDATION, THE INDUSTRY & ACADEMIC COOPERATION IN CHUNGNAM NATIONAL UNIVERSITY
    Inventors: Bum Joon Park, Nam Chul Ha, Sun Hye Lee, Gyu Yong Song, Jee Hyun Lee
  • Patent number: 9184407
    Abstract: An organic light emitting device including: a first electrode, a hole injection layer on the first electrode, a hole transport layer on the hole injection layer, an organic light emitting layer on the hole transport layer, a first electron transport layer on the organic light emitting layer, a second electron transport layer on the organic light emitting layer, an electron injection layer on the second electron transport layer and a second electrode on the electron injection layer, where the first electron transport layer includes a first material for improving a thermal stability, a second material for improving a luminous efficiency and a third material for reducing a driving voltage, and the second electron transport layer is laminated with the first electron transport layer, and the second electrode faces the first electrode.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: November 10, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sun-Hye Lee, Jae-Bok Kim, Won-Jun Song, Myung-Hwan Kim, Ji-Young Kim, Hye-Lim Shin, Tae-Kyu Shim, Yoon-Kyoo Lee
  • Patent number: 8970025
    Abstract: Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Hun Kim, Jin-Woo Park, Dae-Young Choi, Mi-Yeon Kim, Sun-Hye Lee
  • Publication number: 20150028308
    Abstract: An organic light emitting device including: a first electrode, a hole injection layer on the first electrode, a hole transport layer on the hole injection layer, an organic light emitting layer on the hole transport layer, a first electron transport layer on the organic light emitting layer, a second electron transport layer on the organic light emitting layer, an electron injection layer on the second electron transport layer and a second electrode on the electron injection layer, where the first electron transport layer includes a first material for improving a thermal stability, a second material for improving a luminous efficiency and a third material for reducing a driving voltage, and the second electron transport layer is laminated with the first electron transport layer, and the second electrode faces the first electrode.
    Type: Application
    Filed: July 17, 2014
    Publication date: January 29, 2015
    Inventors: Sun-Hye Lee, Jae-Bok Kim, Won-Jun Song, Myung-Hwan Kim, Ji-Young Kim, Hye-Lim Shin, Tae-Kyu Shim, Yoon-Kyoo Lee
  • Publication number: 20140246786
    Abstract: Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.
    Type: Application
    Filed: May 16, 2014
    Publication date: September 4, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Hun KIM, Jin-Woo PARK, Dae-Young CHOI, Mi-Yeon KIM, Sun-Hye LEE
  • Patent number: 8754515
    Abstract: Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 17, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Hun Kim, Jin-Woo Park, Dae-Young Choi, Mi-Yeon Kim, Sun-Hye Lee
  • Publication number: 20140147866
    Abstract: Provided are compounds for inhibiting Snail-p53 binding and therapeutic agents for cancer including the compounds as an effective component. The Snail-p53 binding inhibitors induce expression of p53 in K-Ras mutant cell lines, thereby enabling effective treatment or prevention of K-Ras mutant cancer, such as, pancreatic cancer, lung cancer, cholangioma, and colon cancer, of which diagnosis or treatment is not easy.
    Type: Application
    Filed: December 31, 2013
    Publication date: May 29, 2014
    Applicants: THE INDUSTRY & ACADEMIC COOPERATION IN CHUNGNAM NATIONAL UNIVERSITY, PUSAN NATIONAL UNIVERSITY INDUSTRY-UNIVERSITY COOPERATION FOUNDATION
    Inventors: Bum Joon PARK, Nam Chul Ha, Sun Hye Lee, Gyu Yong Song, Jee Hyun Lee
  • Patent number: 8653640
    Abstract: A semiconductor package apparatus includes a first semiconductor package including a first semiconductor chip, a first substrate, a first terminal, and a first signal transfer medium, and a second semiconductor package including a second semiconductor chip, a second substrate, a second terminal, and a second signal transfer medium. At least one package connecting solder ball is located between the first terminal and the second terminal. A first solder ball guide member is positioned around the first terminal of the first substrate and includes a first guide surface for guiding a shape of the package connecting solder ball.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-hun Kim, Dae-young Choi, Yang-hoon Ahn, Sun-hye Lee
  • Publication number: 20130241044
    Abstract: According to example embodiments, a semiconductor package includes a first semiconductor chip is on a first substrate, a protective layer directly on the first semiconductor chip, and an encapsulant covering an upper surface of the first substrate. The encapsulant may contact side surfaces of the first semiconductor chip and the protective layer.
    Type: Application
    Filed: November 5, 2012
    Publication date: September 19, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Ki KIM, Jung-Do LEE, Yang-Hoon AHN, Sun-Hye LEE, Dae-Young CHOI
  • Publication number: 20130001800
    Abstract: Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 3, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Tae-Hun KIM, Jin-Woo Park, Dae-Young Choi, Mi-Yeon Kim, Sun-Hye Lee
  • Publication number: 20120306075
    Abstract: A semiconductor package apparatus includes a first semiconductor package including a first semiconductor chip, a first substrate, a first terminal, and a first signal transfer medium, and a second semiconductor package including a second semiconductor chip, a second substrate, a second terminal, and a second signal transfer medium. At least one package connecting solder ball is located between the first terminal and the second terminal. A first solder ball guide member is positioned around the first terminal of the first substrate and includes a first guide surface for guiding a shape of the package connecting solder ball.
    Type: Application
    Filed: April 5, 2012
    Publication date: December 6, 2012
    Inventors: TAE-HUN KIM, Dae-young Choi, Yang-hoon Ahn, Sun-hye Lee
  • Patent number: 8293580
    Abstract: Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: October 23, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Hun Kim, Jin-Woo Park, Dae-Young Choi, Mi-Yeon Kim, Sun-Hye Lee
  • Publication number: 20120015960
    Abstract: Provided are compounds for inhibiting Snail-p53 binding and therapeutic agents for cancer including the compounds as an effective component. The Snail-p53 binding inhibitors induce expression of p53 in K-Ras mutant cell lines, thereby enabling effective treatment or prevention of K-Ras mutant cancer, such as, pancreatic cancer, lung cancer, cholangioma, and colon cancer, of which diagnosis or treatment is not easy.
    Type: Application
    Filed: November 23, 2009
    Publication date: January 19, 2012
    Applicants: The Industry & Academic Cooperation in Chungnam National University, Pusan National University Industry-University Cooperation Foundation
    Inventors: Bum Joon Park, Nam Chul Ha, Sun Hye Lee, Gyu Yong Song, Jee Hyun Lee
  • Publication number: 20110291294
    Abstract: A multi-chip package may include a first semiconductor package, a second semiconductor package and an interposer chip. The second semiconductor package may be arranged over the first semiconductor package. The interposer chip may be interposed between the first semiconductor package and the second semiconductor package. The interposer chip may have a receiving groove configured to receive the first semiconductor package. Thus, electrical connection reliability between the first semiconductor package and the second semiconductor package may be improved under a condition that the connecting terminals may have small sizes.
    Type: Application
    Filed: March 16, 2011
    Publication date: December 1, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uk Kim, Jin-woo Park, Dae-Young Choi, Mi-Yeon Kim, Sun-Hye Lee
  • Publication number: 20110237027
    Abstract: Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.
    Type: Application
    Filed: February 15, 2011
    Publication date: September 29, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Hun Kim, Jin-Woo Park, Dae-Young Choi, Mi-Yeon Kim, Sun-Hye Lee