Patents by Inventor Sun-Hyuck Yon

Sun-Hyuck Yon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8331190
    Abstract: A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: December 11, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sun-Hyuck Yon, Kee-Teok Park
  • Publication number: 20110255356
    Abstract: A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode.
    Type: Application
    Filed: June 29, 2011
    Publication date: October 20, 2011
    Inventors: Sun-Hyuck Yon, Kee-Teok Park
  • Patent number: 7995416
    Abstract: A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: August 9, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sun-Hyuck Yon, Kee-Teok Park
  • Patent number: 7710178
    Abstract: A delay apparatus for a delay locked loop includes a plurality of delay devices that are formed by modeling a plurality of signal processing structures through which a delay locked loop clock output from a delay locked loop reaches an output circuit of a semiconductor memory apparatus from an output terminal of the delay locked loop. At least one of the plurality of delay devices is composed of a variable delay device in which a delay time varies according to a change in operation voltage.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: May 4, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sun-Hyuck Yon
  • Publication number: 20090168584
    Abstract: A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode.
    Type: Application
    Filed: June 30, 2008
    Publication date: July 2, 2009
    Applicant: HYNIX SEMICONDUCTOR, INC.
    Inventors: Sun-Hyuck YON, Kee-Teok Park