Patents by Inventor Sun Il Shim

Sun Il Shim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220028740
    Abstract: A vertical memory device includes first gate electrodes stacked on a cell region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel extending through the first gate electrodes and extending in the vertical direction, a first contact plug structure contacting a corresponding one of the first gate electrodes, extending in the vertical direction, and including a first metal pattern, a first barrier pattern covering a lower surface and a sidewall of the first metal pattern and a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern, and a second contact plug structure extending in the vertical direction on a peripheral circuit region of the substrate and including a second metal pattern and a second barrier pattern covering a lower surface and a sidewall of the second metal pattern.
    Type: Application
    Filed: October 13, 2021
    Publication date: January 27, 2022
    Inventors: Shin-Hwan KANG, SUN-IL SHIM, SEUNG HYUN
  • Publication number: 20210391340
    Abstract: A semiconductor memory device includes gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, an upper insulation layer arranged on an uppermost gate electrode, channel structures penetrating through the upper insulation layer, and the gate electrodes in the first direction, and string selection line cut insulation layers horizontally separating the upper insulation layer and the uppermost gate electrode. Each of the string selection line cut insulation layers includes a protrusion protruding toward the uppermost gate electrode and positioning on the same level as the first gate electrode.
    Type: Application
    Filed: August 27, 2021
    Publication date: December 16, 2021
    Inventors: Hae-min LEE, Kwang-soo KIM, Sun-il SHIM
  • Patent number: 11171151
    Abstract: A vertical memory device includes first gate electrodes stacked on a cell region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel extending through the first gate electrodes and extending in the vertical direction, a first contact plug structure contacting a corresponding one of the first gate electrodes, extending in the vertical direction, and including a first metal pattern, a first barrier pattern covering a lower surface and a sidewall of the first metal pattern and a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern, and a second contact plug structure extending in the vertical direction on a peripheral circuit region of the substrate and including a second metal pattern and a second barrier pattern covering a lower surface and a sidewall of the second metal pattern.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: November 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shin-Hwan Kang, Sun-Il Shim, Seung Hyun
  • Publication number: 20210295895
    Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.
    Type: Application
    Filed: June 8, 2021
    Publication date: September 23, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sun-Il Shim, Jae-Hoon Jang, Donghyuk Chae, Youngho Lim, Hansoo Kim, Jaehun Jeong
  • Patent number: 11107826
    Abstract: A semiconductor memory device includes gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, an upper insulation layer arranged on an uppermost gate electrode, channel structures penetrating through the upper insulation layer, and the gate electrodes in the first direction, and string selection line cut insulation layers horizontally separating the upper insulation layer and the uppermost gate electrode. Each of the string selection line cut insulation layers includes a protrusion protruding toward the uppermost gate electrode and positioning on the same level as the first gate electrode.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: August 31, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hae-min Lee, Kwang-soo Kim, Sun-il Shim
  • Patent number: 11062784
    Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: July 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Il Shim, Jae-Hoon Jang, Donghyuk Chae, Youngho Lim, Hansoo Kim, Jaehun Jeong
  • Patent number: 11024638
    Abstract: A three-dimensional semiconductor device includes a first substrate, a second substrate on the first substrate, the second substrate including pattern portions and a plate portion covering the pattern portions, the plate portion having a width greater than a width of each of the pattern portions and being connected to the pattern portions, a lower structure between the first substrate and the second substrate, horizontal conductive patterns on the second substrate, the horizontal conductive patterns being stacked while being spaced apart from each other in a direction perpendicular to an upper surface of the second substrate, and a vertical structure on the second substrate and having a side surface opposing the horizontal conductive patterns.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: June 1, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun Il Shim, Kyung Dong Kim, Ju Hak Song, Jee Hoon Han
  • Patent number: 10983884
    Abstract: A non-volatile memory device may replace a defective string selection line connected to a defective string of a defective memory block among a plurality of memory blocks with a replacement string selection line of a repair memory block; and access the replacement string selection line of the repair memory block instead of the defective string selection line of the defective memory block. The non-volatile memory device performs a repair operation in units of string selection lines and may efficiently use repair resources.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: April 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sun Il Shim
  • Publication number: 20200286530
    Abstract: A semiconductor memory device includes gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, an upper insulation layer arranged on an uppermost gate electrode, channel structures penetrating through the upper insulation layer, and the gate electrodes in the first direction, and string selection line cut insulation layers horizontally separating the upper insulation layer and the uppermost gate electrode. Each of the string selection line cut insulation layers includes a protrusion protruding toward the uppermost gate electrode and positioning on the same level as the first gate electrode.
    Type: Application
    Filed: September 10, 2019
    Publication date: September 10, 2020
    Inventors: Hae-min LEE, Kwang-soo KIM, Sun-il SHIM
  • Publication number: 20200234782
    Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.
    Type: Application
    Filed: April 9, 2020
    Publication date: July 23, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sun-Il SHIM, Jae-Hoon JANG, Donghyuk CHAE, Youngho LIM, Hansoo KIM, Jaehun JEONG
  • Patent number: 10650903
    Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 12, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Il Shim, Jae-Hoon Jang, Donghyuk Chae, Youngho Lim, Hansoo Kim, Jaehun Jeong
  • Publication number: 20200075608
    Abstract: A three-dimensional semiconductor device includes a first substrate, a second substrate on the first substrate, the second substrate including pattern portions and a plate portion covering the pattern portions, the plate portion having a width greater than a width of each of the pattern portions and being connected to the pattern portions, a lower structure between the first substrate and the second substrate, horizontal conductive patterns on the second substrate, the horizontal conductive patterns being stacked while being spaced apart from each other in a direction perpendicular to an upper surface of the second substrate, and a vertical structure on the second substrate and having a side surface opposing the horizontal conductive patterns.
    Type: Application
    Filed: May 22, 2019
    Publication date: March 5, 2020
    Inventors: Sun IL SHIM, Kyung Dong KIM, Ju Hak SONG, Jee Hoon HAN
  • Publication number: 20200043943
    Abstract: A vertical memory device includes first gate electrodes stacked on a cell region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel extending through the first gate electrodes and extending in the vertical direction, a first contact plug structure contacting a corresponding one of the first gate electrodes, extending in the vertical direction, and including a first metal pattern, a first barrier pattern covering a lower surface and a sidewall of the first metal pattern and a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern, and a second contact plug structure extending in the vertical direction on a peripheral circuit region of the substrate and including a second metal pattern and a second barrier pattern covering a lower surface and a sidewall of the second metal pattern.
    Type: Application
    Filed: March 15, 2019
    Publication date: February 6, 2020
    Inventors: Shin-Hwan KANG, SUN-IL SHIM, SEUNG HYUN
  • Publication number: 20190138414
    Abstract: A non-volatile memory device may replace a defective string selection line connected to a defective string of a defective memory block among a plurality of memory blocks with a replacement string selection line of a repair memory block; and access the replacement string selection line of the repair memory block instead of the defective string selection line of the defective memory block. The non-volatile memory device performs a repair operation in units of string selection lines and may efficiently use repair resources.
    Type: Application
    Filed: August 23, 2018
    Publication date: May 9, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Sun Il Shim
  • Publication number: 20190096495
    Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.
    Type: Application
    Filed: November 30, 2018
    Publication date: March 28, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sun-Il SHIM, Jae-Hoon JANG, Donghyuk CHAE, Youngho LIM, Hansoo KIM, Jaehun JEONG
  • Patent number: 10199116
    Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: February 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Il Shim, Jae-Hoon Jang, Donghyuk Chae, Youngho Lim, Hansoo Kim, Jaehun Jeong
  • Patent number: 10134756
    Abstract: A semiconductor device includes a plurality of cell gate electrodes on a semiconductor substrate. End portions of the cell gate electrodes include stepped-pad regions that extend in a direction parallel to a surface of the semiconductor substrate. Vertical structures are on the semiconductor substrate and pass through the plurality of cell gate electrodes. The vertical structures respectively include a channel layer. Upper peripheral transistors are disposed on the semiconductor substrate. The upper peripheral transistors include an upper peripheral gate electrode at a level higher than a level of the plurality of cell gate electrodes, body patterns passing through the upper peripheral gate electrode and electrically connected to the pad regions, and gate dielectric layers between the upper peripheral gate electrode and the body patterns.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: November 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun Il Shim, Seung Wook Choi
  • Publication number: 20180166461
    Abstract: A semiconductor device includes a plurality of cell gate electrodes on a semiconductor substrate. End portions of the cell gate electrodes include stepped-pad regions that extend in a direction parallel to a surface of the semiconductor substrate. Vertical structures are on the semiconductor substrate and pass through the plurality of cell gate electrodes. The vertical structures respectively include a channel layer. Upper peripheral transistors are disposed on the semiconductor substrate. The upper peripheral transistors include an upper peripheral gate electrode at a level higher than a level of the plurality of cell gate electrodes, body patterns passing through the upper peripheral gate electrode and electrically connected to the pad regions, and gate dielectric layers between the upper peripheral gate electrode and the body patterns.
    Type: Application
    Filed: May 30, 2017
    Publication date: June 14, 2018
    Inventors: Sun Il SHIM, Seung Wook Choi
  • Patent number: 9966115
    Abstract: A vertical non-volatile memory device includes a substrate, and a first stack of word lines and a second stack of word lines extending in a first direction on the substrate and separated from each other in a second direction perpendicular to the first direction. The device further includes first array lines extending in the second direction on the first and the second stack, and connected to word lines of the first and the second stack through at least two of first via contacts in a same level. The device further include first word select lines being in a same level and extending in the first direction, and connected to each of the first array lines through at least one of second via contacts. Ends of each of the first and the second stack have a form of stairs on the substrate.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: May 8, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Hwang, Han-Soo Kim, Won-Seok Cho, Jae-Hoon Jang, Sun-Il Shim, Jae-Hun Jeong, Ki-Hyun Kim
  • Publication number: 20170330632
    Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.
    Type: Application
    Filed: July 31, 2017
    Publication date: November 16, 2017
    Inventors: Sun-Il SHIM, Jae-Hoon JANG, Donghyuk CHAE, Youngho LIM, Hansoo KIM, Jaehun JEONG