Abstract: Provided is a method of operating a terminal. The method includes determining a profile item applicable to the profile view for the account based on an input received by the terminal and a coordinate indicating a position where the profile item is provided on the profile view. The method includes displaying the profile item on a screen of the terminal based on the determined profile item and the determined coordinate. The method includes receiving an input related to the profile item, and displaying a visual effect corresponding to the input on the screen.

Abstract: A method of a terminal may comprise: receiving, from a CU of a base station, configuration information of one or more candidate cells and configuration information for measurement; performing L1 measurement on the candidate cells based on the configuration information for measurement; acquiring uplink synchronization for the candidate cells by performing an uplink synchronization management procedure for the candidate cells based on the configuration information of the candidate cells; reporting a result of the L1 measurement to a DU of the base station; receiving, from the DU of the base station, information on a target cell, being the target cell to switch among the candidate cells, based on the result of the L1 measurement; and applying the uplink synchronization acquired through the uplink synchronization management procedure to the target cell.

Abstract: A multilayer capacitor includes a body including dielectric layers and internal electrodes and external electrodes disposed on an external surface of the body and connected to the internal electrodes. The body includes a first surface and a second surface to which the internal electrodes are exposed, the first surface and the second surface opposing each other in a first direction, a third surface and a fourth surface opposing each other in a second direction which is a direction in which the dielectric layers are stacked, and a fifth surface and a sixth surface opposing each other in a third direction. At least one of the internal electrodes include a first bottleneck structure having a first directional length of a third-directional outer region smaller than an inner region thereof and a second bottleneck structure having a third directional length of a first directional outer region smaller than an inner region thereof.

Abstract: In accordance with the present invention, there is provided a punch quad flat no leads (QFN) semiconductor package including a leadframe wherein the leads of the leadframe are selectively half-etched so that only one or more prescribed leads may be electrically connected to a conformal shield applied to the package body of the semiconductor package. The conformal shield may be electrically connected to the exposed lead(s) alone, or in combination with one or more tie bars of the leadframe. In one embodiment, outer end portions of the top surfaces of the leads of the semiconductor package are alternately exposed and non-exposed, with the non-exposed leads including a top side half-etch which causes the same to be effectively covered by the package body of the semiconductor package.

Abstract: In accordance with the present invention, there is provided a punch quad flat no leads (QFN) semiconductor package including a leadframe wherein the leads of the leadframe are selectively half-etched so that only one or more prescribed leads may be electrically connected to a conformal shield applied to the package body of the semiconductor package. The conformal shield may be electrically connected to the exposed lead(s) alone, or in combination with one or more tie bars of the leadframe. In one embodiment, outer end portions of the top surfaces of the leads of the semiconductor package are alternately exposed and non-exposed, with the non-exposed leads including a top side half-etch which causes the same to be effectively covered by the package body of the semiconductor package.

Abstract: A semiconductor package comprising a die paddle defining multiple corners and opposed first and second surfaces. At least one set of leads extends at least partially about the die paddle in spaced relation thereto. Each of the leads has opposed first and second surfaces. Attached to and extending from one of the corners of the die paddle is at least one tie bar which itself has opposed first and second surfaces and at least one aperture disposed therein and extending between the first and second surfaces thereof. Attached to the first surface of the die paddle is a semiconductor die which is electrically connected to at least one of the leads. A package body at least partially covers the die paddle, the leads, the tie bar and the semiconductor die such that the second surfaces of the leads are exposed in and substantially flush with a common exterior surface of the package body, and a portion of the package body extends through the aperture of the tie bar.

Abstract: A printed circuit board for a semiconductor package, a semiconductor package, and methods for manufacturing the same are disclosed. One printed circuit board includes a core layer with circuit patterns formed thereon. The circuit patterns do not extend to a periphery of the circuit board. Each circuit pattern includes a bond finger and/or an input/output land. A solder mask is provided over the circuit patterns, except for bond fingers and lands. A first metal layer is plated only on the horizontal outer surface of the bond finger and/or ball land of the respective circuit pattern, and not over the remainder of the circuit pattern. The localized plating of the first metal layer enhances adhesion of the solder mask to the circuit patterns, enhances adhesion of an encapsulant to the bond fingers, and avoids waste of the first metal layer material.