Patents by Inventor Sun-Ki YUN

Sun-Ki YUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230284378
    Abstract: A storage device includes a printed circuit board including a controller site, a first memory site, a second memory site, first conductive lines connected with the controller site, second conductive lines connected with the first memory site, and third conductive lines connected with the second memory site, a controller package provided on the controller site, a first nonvolatile memory package provided on the first memory site, a second nonvolatile memory package provided on the second memory site, and at least one resistor connecting at least one conductive line of the first conductive lines with at least one conductive line of the second conductive lines.
    Type: Application
    Filed: January 30, 2023
    Publication date: September 7, 2023
    Applicant: SAMSUNG ELECTRONICS CO., LTD
    Inventors: Sun-Ki YUN, Hwi-Jong Yoo, Jeonggi Yoon
  • Patent number: 11277916
    Abstract: A memory system includes a printed circuit board, at least one memory chip mounted on the printed circuit board, and a memory controller arranged on the printed circuit board and connected to 2N (where N is an integer of 2 or more) channels, the memory controller configured to perform a write operation and a read operation on the at least one memory chip. In the printed circuit board, a first subset of the channels corresponds to a first channel group configured in a point to point topology, and a remaining subset of the channels corresponds to a second channel group configured in a daisy chain topology.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: March 15, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-guk Seo, Sun-ki Yun, Su-jin Kim, Hwi-jong Yoo, Young-rok Oh
  • Publication number: 20210022249
    Abstract: A memory system includes a printed circuit board, at least one memory chip mounted on the printed circuit board, and a memory controller arranged on the printed circuit board and connected to 2N (where N is an integer of 2 or more) channels, the memory controller configured to perform a write operation and a read operation on the at least one memory chip. In the printed circuit board, a first subset of the channels corresponds to a first channel group configured in a point to point topology, and a remaining subset of the channels corresponds to a second channel group configured in a daisy chain topology.
    Type: Application
    Filed: October 1, 2020
    Publication date: January 21, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Byung-guk SEO, Sun-ki YUN, Su-jin KIM, Hwi-jong YOO, Young-rok OH
  • Patent number: 10820419
    Abstract: A memory system includes a printed circuit board, at least one memory chip mounted on the printed circuit board, and a memory controller arranged on the printed circuit board and connected to 2N (where N is an integer of 2 or more) channels, the memory controller configured to perform a write operation and a read operation on the at least one memory chip. In the printed circuit board, a first subset of the channels corresponds to a first channel group configured in a point to point topology, and a remaining subset of the channels corresponds to a second channel group configured in a daisy chain topology.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: October 27, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-guk Seo, Sun-ki Yun, Su-jin Kim, Hwi-jong Yoo, Young-rok Oh
  • Publication number: 20190373730
    Abstract: A memory system includes a printed circuit board, at least one memory chip mounted on the printed circuit board, and a memory controller arranged on the printed circuit board and connected to 2N (where N is an integer of 2 or more) channels, the memory controller configured to perform a write operation and a read operation on the at least one memory chip. In the printed circuit board, a first subset of the channels corresponds to a first channel group configured in a point to point topology, and a remaining subset of the channels corresponds to a second channel group configured in a daisy chain topology.
    Type: Application
    Filed: December 3, 2018
    Publication date: December 5, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Byung-guk SEO, Sun-ki YUN, Su-jin KIM, Hwi-jong YOO, Young-rok OH
  • Patent number: 10437766
    Abstract: A data storage device is provided. The data store device includes a first printed circuit board (PCB) comprising a main transmission line formed on at least one surface of the first PCB and/or within the first PCB, a memory controller and a plurality of nonvolatile memory devices. The memory controller is provided on the first PCB. The plurality of nonvolatile memory devices are provided on the first PCB. The plurality of nonvolatile memory devices are connected to the memory controller through a channel and exchange data with the memory controller. The channel includes a data transmission line connecting data pads of the memory controller and the nonvolatile memory devices. The data transmission line comprises the main transmission pattern and an open stub contacting the main transmission pattern. The open stub does not contact any other conductor other than the main transmission pattern.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: October 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Woon Park, Sun-Ki Yun, Kwang-Soo Park
  • Publication number: 20180018294
    Abstract: A data storage device is provided. The data store device includes a first printed circuit board (PCB) comprising a main transmission line formed on at least one surface of the first PCB and/or within the first PCB, a memory controller and a plurality of nonvolatile memory devices. The memory controller is provided on the first PCB. The plurality of nonvolatile memory devices are provided on the first PCB. The plurality of nonvolatile memory devices are connected to the memory controller through a channel and exchange data with the memory controller. The channel includes a data transmission line connecting data pads of the memory controller and the nonvolatile memory devices. The data transmission line comprises the main transmission pattern and an open stub contacting the main transmission pattern. The open stub does not contact any other conductor other than the main transmission pattern.
    Type: Application
    Filed: June 15, 2017
    Publication date: January 18, 2018
    Inventors: Ji-Woon PARK, Sun-Ki YUN, Kwang-Soo PARK