Abstract: An improved UART which has a number of channels, with each channel having a set of channel configuration registers. Each channel configuration register includes an interrupt source register. The interrupt source register has a multi-bit interrupt source code which is used to indicate the source of the interrupt. This code is chosen to be compatible with prior UART devices. The device also includes a bus interface, and a plurality of device configuration registers accessible through the bus interface by a user. One of the device configuration registers is an interrupt register which provides a user accessible code to indicate the interrupt source. The code used for the interrupt source is a compressed version of the multiple bit code used in the channel configuration interrupt source register. This compression allows more channels to be represented in a single register, while also conveying the interrupt source information quickly to the user.

Abstract: A UART with a FIFO buffer is provided. A circuit detects a last word transmitted from the FIFO buffer. A transmitter empty circuit generates a transmitter empty signal (RTS) when the last word transmitted from the FIFO buffer is detected. A delay circuit delays generation of the RTS signal for a programmable time delay. The time delay via a register that is programmable by the user. The invention thus provides the programmable delay on the same chip as the UART.