Patents by Inventor Sun-Mo Hwang

Sun-Mo Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154147
    Abstract: An apparatus for manufacturing a pouch-type rechargeable battery includes a preforming portion forming a folding groove in a portion of a protrusion of the pouch-type rechargeable battery, a folding portion disposed on a rear end of the preforming portion and folding the protrusion along the folding groove, a rolling portion disposed on a rear end of the folding portion and pressing the folded protrusion, and a pressing portion disposed on a rear end of the rolling portion and fixing the folded protrusion.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 9, 2024
    Inventors: Seung Won Choi, Dong Ju Kim, Sun Min Park, Sang Mo Kim, Jae Gyu Byun, Won Je Oh, Taek Eon Jeong, Ju Won Hwang
  • Patent number: 9972382
    Abstract: A non-volatile memory device according to example embodiments includes at least one NAND flash memory and a memory controller configured to control the NAND flash memory. The memory controller comprises a bit counter configured to count a number of first binary digit of each of first to N-th readout page data, the first to N-th readout page data being respectively read by first to N-th test read voltages, a register configured to store first to N-th count values with respect to the first to N-th readout page data output from the bit counter, and a read voltage adjuster configured to compare the first to N-th count values to determine a read voltage, where N is an integer greater than 1.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: May 15, 2018
    Assignee: The-AiO Inc.
    Inventors: Seung-Hyun Han, Sun-Mo Hwang
  • Patent number: 9558816
    Abstract: A method of adjusting read voltages for a NAND flash memory device includes an operation of reading first page data from a first page corresponding to a paired page of a second page, an operation of simultaneously changing the first test read voltage and the third test read voltage to read second page data from a second page, an operation of performing a bitwise operation on the first page data and the second page data an operation of counting a number of memory cells corresponding to a first threshold voltage state and a fourth threshold voltage state by using a result of the bitwise operation, and an operation of setting a first read voltage and a third read voltage as a voltage corresponding to a section in which a change in the number of memory cells is a lowest value.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: January 31, 2017
    Assignee: The-AiO Inc.
    Inventors: Seung-Hyun Han, Sun-Mo Hwang
  • Publication number: 20160300609
    Abstract: A non-volatile memory device according to example embodiments includes at least one NAND flash memory and a memory controller configured to control the NAND flash memory. The memory controller comprises a bit counter configured to count a number of first binary digit of each of first to N-th readout page data, the first to N-th readout page data being respectively read by first to N-th test read voltages, a register configured to store first to N-th count values with respect to the first to N-th readout page data output from the bit counter, and a read voltage adjuster configured to compare the first to N-th count values to determine a read voltage, where N is an integer greater than 1.
    Type: Application
    Filed: October 6, 2014
    Publication date: October 13, 2016
    Applicant: The-AiO Inc.
    Inventors: Seung-Hyun Han, Sun-Mo Hwang
  • Publication number: 20160225440
    Abstract: A method of adjusting read voltages for a NAND flash memory device includes an operation of reading first page data from a first page corresponding to a paired page of a second page, an operation of simultaneously changing the first test read voltage and the third test read voltage to read second page data from a second page, an operation of performing a bitwise operation on the first page data and the second page data an operation of counting a number of memory cells corresponding to a first threshold voltage state and a fourth threshold voltage state by using a result of the bitwise operation, and an operation of setting a first read voltage and a third read voltage as a voltage corresponding to a section in which a change in the number of memory cells is a lowest value.
    Type: Application
    Filed: June 27, 2014
    Publication date: August 4, 2016
    Applicant: The-AiO Inc.
    Inventors: Seung-Hyun Han, Sun-Mo Hwang
  • Patent number: 9286996
    Abstract: A non-volatile memory system includes a first non-volatile memory device, a second non-volatile memory device that performs a write operation more slowly than the first non-volatile memory device, where the first and second non-volatile memory devices are different types of non-volatile memory devices, and a controller that controls the first and second non-volatile memory devices to concurrently perform the write operation for data input from a host based on a write command signal and that outputs a write completion signal to the host when one of the first and second non-volatile memory devices completes the write operation.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: March 15, 2016
    Assignee: The AiO Inc.
    Inventor: Sun-Mo Hwang
  • Publication number: 20150193157
    Abstract: A method of reading page data of a NAND flash memory device is provided. By the method, a plurality of page data that are read from a memory cell array of the NAND flash memory device are stored in a plurality of page buffers, respectively, buffer output data is generated by selecting respective portions of the page data in a vertical direction with respect to the page buffers, and then the buffer output data is output to a memory controller. Thus, the method may enable a memory system including the NAND flash memory device to operate at a high speed while achieving high reliability for the page data.
    Type: Application
    Filed: April 18, 2013
    Publication date: July 9, 2015
    Inventor: Sun-Mo Hwang
  • Publication number: 20150127889
    Abstract: A non-volatile memory system includes a NAND flash memory device including a first flash translation layer that performs a garbage collection operation, and a host device including a file system and a second flash translation layer that controls an operation of the NAND flash memory device by interacting with the file system. Here, the host device provides application data in an in-ordered form to the NAND flash memory device. Thus, the non-volatile memory system can perform a random write operation at high speed, and can minimize power consumption due to unnecessary data transfer.
    Type: Application
    Filed: April 18, 2013
    Publication date: May 7, 2015
    Applicant: THE-AIO INC.
    Inventor: Sun-Mo Hwang
  • Publication number: 20140362648
    Abstract: A non-volatile memory system includes a first non-volatile memory device, a second non-volatile memory device that performs a write operation more slowly than the first non-volatile memory device, where the first and second non-volatile memory devices are different types of non-volatile memory devices, and a controller that controls the first and second non-volatile memory devices to concurrently perform the write operation for data input from a host based on a write command signal and that outputs a write completion signal to the host when one of the first and second non-volatile memory devices completes the write operation.
    Type: Application
    Filed: December 6, 2012
    Publication date: December 11, 2014
    Applicant: THE-AIO INC.
    Inventor: Sun-Mo Hwang