Abstract: A semiconductor chip includes a first semiconductor device and a second semiconductor device stacked over the first semiconductor device. The second semiconductor device is electrically connected to the first semiconductor device via a plurality of through electrodes. In a test mode, the first semiconductor device is configured to drive a first pattern of logic levels and a second pattern of logic levels through the plurality of through electrodes, configured to compare logic levels of a plurality of test data generated by the first and second patterns from the first and second semiconductor devices to generate a detection signal indicating that the plurality of through electrodes operated normally or abnormally.

Abstract: An electronic device includes a replica delay circuit configured to generate a delayed error check signal by delaying a first error check signal including error information of first data stored in a first memory region. The electronic device also includes an error sum signal generation circuit configured to generate an error sum signal by summing a second error check signal including error information of second data stored in a second memory region and the delayed error check signal.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs an error check enablement signal, an input clock signal, and input data to the second semiconductor device. The first semiconductor device receives an error check signal from the second semiconductor device. The second semiconductor device performs an error check operation for the input data based on the error check enablement signal and the input clock signal to generate the error check signal which is enabled when an error in the input data occurs.

Abstract: A semiconductor device includes an error detection circuit configured to generate fixed data by fixing any one of a first group and a second group included in internal data to a preset level based on a burst chop signal and an internal command address in response to a read command, and generate an error detection signal by detecting an error of the fixed data; and a data output circuit configured to generate latch data by latching the internal data based on a first latch output control signal, and generate output data by serializing the latch data and the error detection signal based on a second latch output control signal.

Abstract: An electronic device includes a replica delay circuit configured to generate a delayed error check signal by delaying a first error check signal including error information of first data stored in a first memory region. The electronic device also includes an error sum signal generation circuit configured to generate an error sum signal by summing a second error check signal including error information of second data stored in a second memory region and the delayed error check signal.

Abstract: A semiconductor device includes a master chip and a first slave chip. The master chip outputs a write signal or read signal and a chip identification (ID) signal and outputs data through a transmitter activated by the write signal or receives data through a receiver activated by the read signal. The first slave chip enters a write operation according to the write signal and activates a first receiver to store the data when the chip ID signal has a first logic level combination. The first slave chip enters a read operation according to the read signal and configured to activate a first transmitter to output the data when the chip ID signal has a first logic level combination. The master chip and the first slave chip are vertically stacked and are electrically connected to each other by a plurality of through electrodes penetrating the first slave chip.

Abstract: A semiconductor chip includes a first semiconductor device and a second semiconductor device stacked over the first semiconductor device. The second semiconductor device is electrically connected to the first semiconductor device via a plurality of through electrodes. In a test mode, the first semiconductor device is configured to drive a first pattern of logic levels and a second pattern of logic levels through the plurality of through electrodes configured to compare logic levels of a plurality of test data generated by the first and second patterns from the first and second semiconductor devices to generate a detection signal indicating that the plurality of through electrodes operated normally or abnormally.

Abstract: A semiconductor chip includes a first semiconductor device and a second semiconductor device stacked over the first semiconductor device. The second semiconductor device is electrically connected to the first semiconductor device via a plurality of through electrodes. In a test mode, the first semiconductor device is configured to drive a first pattern of logic levels and a second pattern of logic levels through the plurality of through electrodes, configured to compare logic levels of a plurality of test data generated by the first and second patterns from the first and second semiconductor devices to generate a detection signal indicating that the plurality of through electrodes operated normally or abnormally.

Abstract: A semiconductor system including a semiconductor device configured to operate in various modes to generate output data having different patterns.

Abstract: A semiconductor device includes a master chip and a first slave chip. The master chip outputs a write signal or read signal and a chip identification (ID) signal and outputs data through a transmitter activated by the write signal or receives data through a receiver activated by the read signal. The first slave chip enters a write operation according to the write signal and activates a first receiver to store the data when the chip ID signal has a first logic level combination. The first slave chip enters a read operation according to the read signal and configured to activate a first transmitter to output the data when the chip ID signal has a first logic level combination. The master chip and the first slave chip are vertically stacked and are electrically connected to each other by a plurality of through electrodes penetrating the first slave chip.

Abstract: A semiconductor chip includes a first semiconductor device and a second semiconductor device stacked and coupled through a unidirectional through electrode and a plurality of bidirectional through electrodes, wherein a through electrode in which a failure has occurred among the unidirectional through electrode and the plurality of bidirectional through electrodes is replaced based on a plurality of transfer control signals. The plurality of transfer control signals including failure information on the unidirectional through electrode and the plurality of bidirectional through electrodes.

Abstract: A semiconductor chip includes a first semiconductor device and a second semiconductor device stacked and coupled through a unidirectional through electrode and a plurality of bidirectional through electrodes, wherein a through electrode in which a failure has occurred among the unidirectional through electrode and the plurality of bidirectional through electrodes is replaced based on a plurality of transfer control signals. The plurality of transfer control signals including failure information on the unidirectional through electrode and the plurality of bidirectional through electrodes.

Abstract: A semiconductor chip includes a first semiconductor device and a second semiconductor device stacked over the first semiconductor device. The second semiconductor device is electrically connected to the first semiconductor device via a plurality of through electrodes. In a test mode, the first semiconductor device is configured to drive a first pattern of logic levels and a second pattern of logic levels through the plurality of through electrodes, configured to compare logic levels of a plurality of test data generated by the first and second patterns from the first and second semiconductor devices to generate a detection signal indicating that the plurality of through electrodes operated normally or abnormally.

Abstract: A semiconductor device includes an error detection circuit configured to generate fixed data by fixing any one of a first group and a second group included in internal data to a preset level based on a burst chop signal and an internal command address in response to a read command, and generate an error detection signal by detecting an error of the fixed data; and a data output circuit configured to generate latch data by latching the internal data based on a first latch output control signal, and generate output data by serializing the latch data and the error detection signal based on a second latch output control signal.

Abstract: A semiconductor chip includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes an error detection circuit. The second semiconductor device is stacked with the first semiconductor device and is electrically connected to the first semiconductor device via a first through electrode and a second through electrode. The first and second semiconductor devices are configured to receive or output first data and second data via the second through electrode according to an operation mode and are configured to detect errors of the first data and the second data using the error detection circuit.

Abstract: A semiconductor system including a semiconductor device configured to operate in various modes to generate output data having different patterns.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs an error check enablement signal, an input clock signal, and input data to the second semiconductor device. The first semiconductor device receives an error check signal from the second semiconductor device. The second semiconductor device performs an error check operation for the input data based on the error check enablement signal and the input clock signal to generate the error check signal which is enabled when an error in the input data occurs.

Abstract: A semiconductor device includes a shift register and a control signal generation circuit. The shift register generates shifted pulses, wherein a number of the shifted pulses is controlled according to a mode of a burst length. The control signal generation circuit generates a control signal for setting a burst operation period according to a period during which the shifted pulses are created. The burst operation period is a period during which a burst operation is performed.

Abstract: A semiconductor device includes a shift register and a control signal generation circuit. The shift register generates shifted pulses, wherein a number of the shifted pulses is controlled according to a mode of a burst length. The control signal generation circuit generates a control signal for setting a burst operation period according to a period during which the shifted pulses are created. The burst operation period is a period during which a burst operation is performed.