Abstract: An array substrate includes a switching device, a storage capacitor and a voltage-dividing capacitor. The switching device is formed in a pixel region defined by two gate lines adjacent to each other and two data lines adjacent to each other. The storage capacitor is electrically connected to the switching device. The voltage-dividing capacitor is disposed between the storage capacitor and one of the gate lines. The voltage-dividing capacitor is electrically connected to the storage capacitor. Therefore, an overlapping area with the data lines is reduced to reduce the RC delay and enhance aperture ratio. Furthermore, a possibility of occurrence of an electrical short is reduced.

Abstract: An array substrate includes a switching device, a storage capacitor and a voltage-dividing capacitor. The switching device is formed in a pixel region defined by two gate lines adjacent to each other and two data lines adjacent to each other. The storage capacitor is electrically connected to the switching device. The voltage-dividing capacitor is disposed between the storage capacitor and one of the gate lines. The voltage-dividing capacitor is electrically connected to the storage capacitor. Therefore, an overlapping area with the data lines is reduced to reduce the RC delay and enhance aperture ratio. Furthermore, a possibility of occurrence of an electrical short is reduced.

Abstract: An array substrate includes a switching device, a storage capacitor and a voltage-dividing capacitor. The switching device is formed in a pixel region defined by two gate lines adjacent to each other and two data lines adjacent to each other. The storage capacitor is electrically connected to the switching device. The voltage-dividing capacitor is disposed between the storage capacitor and one of the gate lines. The voltage-dividing capacitor is electrically connected to the storage capacitor. Therefore, an overlapping area with the data lines is reduced to reduce the RC delay and enhance aperture ratio. Furthermore, a possibility of occurrence of an electrical short is reduced.

Abstract: A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming an ohmic contact layer on the semiconductor layer, and forming a data line including a source electrode and a drain electrode on the ohmic contact layer. The method further includes depositing a conductive film on the data line and the drain electrode, forming a first photoresist on the conductive film, etching the conductive film using the first photoresist as a mask to form a pixel electrode at least connected to the drain electrode, depositing a passivation layer, and removing the first photoresist to form a passivation member.

Abstract: An array substrate includes a switching device, a storage capacitor and a voltage-dividing capacitor. The switching device is formed in a pixel region defined by two gate lines adjacent to each other and two data lines adjacent to each other. The storage capacitor is electrically connected to the switching device. The voltage-dividing capacitor is disposed between the storage capacitor and one of the gate lines. The voltage-dividing capacitor is electrically connected to the storage capacitor. Therefore, an overlapping area with the data lines is reduced to reduce the RC delay and enhance aperture ratio. Furthermore, a possibility of occurrence of an electrical short is reduced.

Abstract: A method of manufacturing a thin film transistor array panel includes forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming an ohmic contact layer on the semiconductor layer, and forming a data line including a source electrode and a drain electrode on the ohmic contact layer. The method further includes depositing a conductive film on the data line and the drain electrode, forming a first photoresist on the conductive film, etching the conductive film using the first photoresist as a mask to form a pixel electrode at least connected to the drain electrode, depositing a passivation layer, and removing the first photoresist to form a passivation member.