Patents by Inventor Sun-Rong Jan

Sun-Rong Jan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Through silicon via layout pattern
    Patent number: 10002820
    Abstract: A semiconductor device comprises a substrate with a first side and a second side, wherein a plurality of active circuits are formed adjacent to the first side of the substrate and a plurality of through silicon vias arranged in a polygon shape and extending from the first side of to the second side, wherein the polygon shape has more than six sides, and wherein each through silicon via is placed at a corresponding apex of the polygon shape.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: June 19, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sun-Rong Jan, Che-Yu Yeh, Chee Wee Liu, Chien-Hua Huang, Bing J. Sheu
  • Through Silicon Via Layout Pattern
    Publication number: 20130221534
    Abstract: A semiconductor device comprises a substrate with a first side and a second side, wherein a plurality of active circuits are formed adjacent to the first side of the substrate and a plurality of through silicon vias arranged in a polygon shape and extending from the first side of to the second side, wherein the polygon shape has more than six sides, and wherein each through silicon via is placed at a corresponding apex of the polygon shape.
    Type: Application
    Filed: May 23, 2012
    Publication date: August 29, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sun-Rong Jan, Che-Yu Yeh, Chee Wee Liu, Chien-Hua Huang, Bing J. Sheu
  • Method with mechanically strained silicon for enhancing speed of integrated circuits or devices
    Patent number: 7307004
    Abstract: A method with a mechanically strained silicon for enhancing the speeds of integrated circuits or devices is disclosed. The method with a mechanically strained silicon for enhancing the speeds of integrated circuits or devices includes the following steps: (a) providing a substrate, (b) fixing the substrate, (c) applying a stress upon the substrate, and (d) inducing a strain in one of a device and a circuit by stressing the substrate.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: December 11, 2007
    Assignee: National Taiwan University
    Inventors: Cheng-Ya Yu, Sun-Rong Jan, Shu-Tong Chang, Chee-Wee Liu
  • Method with mechanically strained silicon for enhancing speed of integrated circuits of devices
    Publication number: 20060099772
    Abstract: A method with a mechanically strained silicon for enhancing the speeds of integrated circuits or devices is disclosed. The method with a mechanically strained silicon for enhancing the speeds of integrated circuits or devices includes the following steps: (a) providing a substrate, (b) fixing the substrate, (c) applying a stress upon the substrate, and (d) inducing a strain in one of a device and a circuit by stressing the substrate.
    Type: Application
    Filed: November 5, 2004
    Publication date: May 11, 2006
    Applicant: National Taiwan University
    Inventors: Cheng-Ya Yu, Sun-Rong Jan, Shu-Tong Chang, Chee-Wee Liu