Patents by Inventor Sun-Soo Shin
Sun-Soo Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9841950Abstract: A modular multiplier and a modular multiplication method are provided. The modular multiplier includes: a first register which stores a previous accumulation value calculated at a previous cycle; a second register which stores a previous quotient calculated at the previous cycle; a quotient generator which generates a quotient using the stored previous accumulation value output from the first register; and an accumulator which receives an operand, a bit value of a multiplier, the stored previous accumulation value, and the stored previous quotient to calculate an accumulation value in a current cycle, wherein the calculated accumulation value is updated to the first register, and the generated quotient is updated to the second register.Type: GrantFiled: August 22, 2016Date of Patent: December 12, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Ki Lee, Jonghoon Shin, KyoungMoon Ahn, Ji-Su Kang, Sun-Soo Shin
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Patent number: 9811318Abstract: A Montgomery multiplier includes a partial product computing unit for multiplying a multiplicand and a multiplier; a modulus reduction computing unit for performing a multiplication of a modulus and a quotient that reflects a quotient sign; an accumulation unit for accumulating in a intermediate value an output value of the partial product computing unit and an output value of the modulus reduction computing unit from a previous cycle; a quotient computing unit for receiving an accumulation value of the accumulation unit during a current cycle and calculating a quotient sign to be used during a next cycle; and a quotient sign determination unit for determining a quotient sign to be used during a next cycle from the multiplicand, the multiplier and the quotient.Type: GrantFiled: March 30, 2015Date of Patent: November 7, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jonghoon Shin, Sun-Soo Shin, Kyoungmoon Ahn, Yong Ki Lee
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Patent number: 9633185Abstract: A method of debugging a device which includes a plurality of processors is provided. The method includes verifying a request to initiate authentication that is provided to the device to a user; performing a challenge-response authentication operation between the user and the device in response to the request to initiate authentication being a request from a non-malicious user; activating or deactivating an access to a Joint Test Action Group (JTAG) port of each of the processors, based on access control information from the user; and permitting a debugging operation via an access that is activated.Type: GrantFiled: December 1, 2014Date of Patent: April 25, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jonghoon Shin, KyoungMoon Ahn, Mijung Noh, Yong Ki Lee, Sun-Soo Shin
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Publication number: 20160357515Abstract: A modular multiplier and a modular multiplication method are provided. The modular multiplier includes: a first register which stores a previous accumulation value calculated at a previous cycle; a second register which stores a previous quotient calculated at the previous cycle; a quotient generator which generates a quotient using the stored previous accumulation value output from the first register; and an accumulator which receives an operand, a bit value of a multiplier, the stored previous accumulation value, and the stored previous quotient to calculate an accumulation value in a current cycle, wherein the calculated accumulation value is updated to the first register, and the generated quotient is updated to the second register.Type: ApplicationFiled: August 22, 2016Publication date: December 8, 2016Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: YONG KI LEE, JONGHOON SHIN, KyoungMoon AHN, Ji-Su KANG, Sun-Soo SHIN
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Patent number: 9448768Abstract: A modular multiplier and a modular multiplication method are provided. The modular multiplier includes: a first register which stores a previous accumulation value calculated at a previous cycle; a second register which stores a previous quotient calculated at the previous cycle; a quotient generator which generates a quotient using the stored previous accumulation value output from the first register; and an accumulator which receives an operand, a bit value of a multiplier, the stored previous accumulation value, and the stored previous quotient to calculate an accumulation value in a current cycle, wherein the calculated accumulation value is updated to the first register, and the generated quotient is updated to the second register.Type: GrantFiled: March 11, 2013Date of Patent: September 20, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Ki Lee, Jonghoon Shin, KyoungMoon Ahn, Ji-Su Kang, Sun-Soo Shin
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Publication number: 20160034255Abstract: Disclosed are arithmetic devices, a method of a Montgomery parameter calculation thereof and a Montgomery multiplication method thereof. The method of the Montgomery parameter calculation of the arithmetic devices includes detecting a position of a most significant bit (MSB) of a modulus, calculating an initial value using position information about the detected MSB, and calculating an intermediate value and a Montgomery parameter by repeatedly performing a Montgomery addition or a Montgomery multiplication with respect to the initial value.Type: ApplicationFiled: May 27, 2015Publication date: February 4, 2016Inventors: Sun-Soo Shin, Jonghoon Shin, KyoungMoon Ahn, Yong Ki Lee
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Patent number: 9164732Abstract: A multiplication method and a modular multiplier are provided. The multiplication method includes transforming a redundant-form multiplier by adding a recoding constant to the multiplier, performing recoding by using the transformed multiplier, and performing partial multiplication between the multiplier and a multiplicand using result values of the recoding.Type: GrantFiled: December 23, 2013Date of Patent: October 20, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Ki Lee, Sun-Soo Shin, Jonghoon Shin, Kyoung Moon Ahn, Ji-Su Kang, Kee Moon Chun
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Publication number: 20150277855Abstract: A Montgomery multiplier includes a partial product computing unit for multiplying a multiplicand and a multiplier; a modulus reduction computing unit for performing a multiplication of a modulus and a quotient that reflects a quotient sign; an accumulation unit for accumulating in a intermediate value an output value of the partial product computing unit and an output value of the modulus reduction computing unit from a previous cycle; a quotient computing unit for receiving an accumulation value of the accumulation unit during a current cycle and calculating a quotient sign to be used during a next cycle; and a quotient sign determination unit for determining a quotient sign to be used during a next cycle from the multiplicand, the multiplier and the quotient.Type: ApplicationFiled: March 30, 2015Publication date: October 1, 2015Inventors: JONGHOON SHIN, SUN-SOO SHIN, KYOUNGMOON AHN, YONG KI LEE
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Publication number: 20150242606Abstract: A method of debugging a device which includes a plurality of processors is provided. The method includes verifying a request to initiate authentication that is provided to the device to a user; performing a challenge-response authentication operation between the user and the device in response to the request to initiate authentication being a request from a non-malicious user; activating or deactivating an access to a Joint Test Action Group (JTAG) port of each of the processors, based on access control information from the user; and permitting a debugging operation via an access that is activated.Type: ApplicationFiled: December 1, 2014Publication date: August 27, 2015Inventors: Jonghoon SHIN, KyoungMoon AHN, Mijung NOH, Yong Ki LEE, Sun-Soo SHIN
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Patent number: 9098381Abstract: A modular arithmetic unit includes a first input generator receiving first data to generate a first operand; a second input generator receiving second data to generate a second operand; an accumulator performing an accumulate/shift operation to add the first and second operands and outputting the carry and sum; a carry propagation adder adding the carry and the sum to output a result; and a data handler receiving either external data or the result and outputting the first data and the second data.Type: GrantFiled: January 4, 2013Date of Patent: August 4, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoungmoon Ahn, Jonghoon Shin, Yong Ki Lee, Ji-Su Kang, Sun-Soo Shin
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Patent number: 9043377Abstract: A Montgomery inverse calculation device includes a plurality of registers each storing a value of a variable, a modulus register storing a modulus, a multiplier performing multiplication on the modulus. A comparator compares the value of the variable stored in each of the registers with an output value of the multiplier and generates a plurality of control signals. A plurality of shifters shifts bits of a value of a variable stored in a corresponding register among the registers in response to at least one first control signal, and a quotient generation block calculates a quotient of mod 2m with respect to values output from some of the shifters in response to a second control signal. A calculation block calculates an updated value of an output value of each of the shifters using the quotient in response to at least one third control signal.Type: GrantFiled: January 30, 2012Date of Patent: May 26, 2015Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Young Sik Kim, Kyoung Moon Ahn, Jong Hoon Shin, Sun-Soo Shin, Ji-Su Kang
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Publication number: 20140192977Abstract: A multiplication method and a modular multiplier are provided. The multiplication method includes transforming a redundant-form multiplier by adding a recoding constant to the multiplier, performing recoding by using the transformed multiplier, and performing partial multiplication between the multiplier and a multiplicand using result values of the recoding.Type: ApplicationFiled: December 23, 2013Publication date: July 10, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Yong Ki LEE, Sun-Soo SHIN, Jonghoon SHIN, Kyoung Moon AHN, Ji-Su KANG, Kee Moon CHUN
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Patent number: 8756268Abstract: A radix-2k Montgomery multiplier including an input coefficient generation unit to receive a multiplier, a multiplicand, a modulus, a sum and a previous sum, to generate and to output a partial product and a multiple modulus by using at least one of the multiplier, the multiplicand, the modulus and the sum, and to divide and to output the received previous sum into units of k bits, an accumulator circuit to receive the partial product, the multiple modulus and k bits of the previous sum from the input coefficient generation unit, and to generate and to output a carry and a sum by summing the partial product, the multiple modulus and the previous sum, and a carry propagation adder (CPA) circuit to generate and to output an ultimate sum by using the carry and the sum.Type: GrantFiled: March 21, 2011Date of Patent: June 17, 2014Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Kyoung-moon Ahn, Young-sik Kim, Jong-hoon Shin, Sun-soo Shin, Ji-su Kang
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Patent number: 8706788Abstract: A modular calculator and a method of performing a modular calculation are provided. The modular calculator includes a first register to receive and to store a first integer, a second register to receive and to store a second integer, a calculator connected to an output terminal of the first register and an output terminal of the second register, and a controller to determine an arithmetic operation of the calculator by referring to a sign of the first integer and a sign of the second integer and to control the calculator to perform the determined arithmetic operation on one of an addition and a subtraction of the first integer and the second integer and a modulus value.Type: GrantFiled: September 23, 2011Date of Patent: April 22, 2014Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Jong Hoon Shin, Kyoung Moon Ahn, Young Sik Kim, Sun-Soo Shin, Ji-Su Kang
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Publication number: 20130311533Abstract: A modular multiplier and a modular multiplication method are provided. The modular multiplier includes: a first register which stores a previous accumulation value calculated at a previous cycle; a second register which stores a previous quotient calculated at the previous cycle; a quotient generator which generates a quotient using the stored previous accumulation value output from the first register; and an accumulator which receives an operand, a bit value of a multiplier, the stored previous accumulation value, and the stored previous quotient to calculate an accumulation value in a current cycle, wherein the calculated accumulation value is updated to the first register, and the generated quotient is updated to the second register.Type: ApplicationFiled: March 11, 2013Publication date: November 21, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong Ki LEE, Jonghoon SHIN, KyoungMoon AHN, Ji-Su KANG, Sun-Soo SHIN
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Publication number: 20130311531Abstract: A modular arithmetic unit includes a first input generator receiving first data to generate a first operand; a second input generator receiving second data to generate a second operand; an accumulator performing an accumulate/shift operation to add the first and second operands and outputting the carry and sum; a carry propagation adder adding the carry and the sum to output a result; and a data handler receiving either external data or the result and outputting the first data and the second data.Type: ApplicationFiled: January 4, 2013Publication date: November 21, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: KYOUNGMOON AHN, Jonghoon Shin, Yong Ki Lee, Ji-su Kang, Sun-soo Shin
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Publication number: 20130262544Abstract: An electronic multiplier, such as a multiplication circuit, may include a partial product generator, a Booth code encoder and an accumulator. The partial product generator may generate partial product data based on a Booth code and multiplicand data. The Booth code encoder may generate the Booth code based on multiplier data. The Booth code may include a zero-generation Booth code and a zero-avoidance Booth code. The Booth code encoder may selectively generate the zero-generation Booth code or the zero-avoidance Booth code when the partial product data correspond to a partial product of zero. The accumulator accumulates the partial product data to provide a multiplication result of the multiplicand data and the multiplier data.Type: ApplicationFiled: December 17, 2012Publication date: October 3, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Ki Lee, Jong-Hoon Shin, Kyoung-Moon Ahn, Ji-Su Kang, Sun-Soo Shin
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Patent number: 8458242Abstract: Provided are a modular multiplier apparatus in which a value of a long path carry (LPC) is predicted to reduce a critical path of an arithmetic operation of Montgomery modular multiplication, and a method of reducing the critical path of the arithmetic operation.Type: GrantFiled: February 25, 2010Date of Patent: June 4, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Young-sik Kim, Mi-jung Noh, Kyoung-moon Ahn, Sun-soo Shin
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Patent number: 8407270Abstract: Provided is a method of calculating a negative inverse of a modulus, wherein the negative inverse, which is an essential element in Montgomery multiplication, is quickly obtained. The method includes setting a modulus, defining P obtained by converting the modulus to a negative number, and defining S obtained by subtracting 1 from P, and calculating a negative inverse of the modulus by using P and S.Type: GrantFiled: November 13, 2009Date of Patent: March 26, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Young-sik Kim, Mi-jung Noh, Kyoung-moon Ahn, Sun-soo Shin
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Publication number: 20120317159Abstract: A modular operator, a smart card including the same, and a method of operating the same are provided. The modular operator includes: an input unit configured to receive first data, second data, and a modulus; and an accumulator configured to perform an accumulation operation on the first data and a first portion of the second data, to shift the accumulation operation result to the right as much as the number of bits of the first portion, and to perform an accumulation operation on a result of a shifted accumulation operation, a second part, of the second data, which is shifted to the right as much as the number of bits of the first portion, and the modulus.Type: ApplicationFiled: April 20, 2012Publication date: December 13, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung Moon Ahn, Jong Hoon Shin, Ji-Su Kang, Sun-Soo Shin