Abstract: A delay adjusting apparatus may include at least one selective delay element electrically coupled to an electrical path between an input terminal and an output terminal of the electrical path, and the at least one selective delay element configured to add a delay factor to the electrical path in response to an enable signal. The delay adjusting apparatus may include at least one fuse circuit configured to control electrical coupling of an e-fuse, in response to a program signal, and program the enable signal.

Abstract: A delay adjusting apparatus may include at least one selective delay element electrically coupled to an electrical path between an input terminal and an output terminal of the electrical path, and the at least one selective delay element configured to add a delay factor to the electrical path in response to an enable signal. The delay adjusting apparatus may include at least one fuse circuit configured to control electrical coupling of an e-fuse, in response to a program signal, and program the enable signal.

Abstract: A semiconductor memory device includes an internal signal generation block configured to generate a control signal which is enabled from a generation time of an internal active signal enabled if it is determined that a combination of external commands in synchronization with a rising edge of an external clock inputted from an outside is a preset combination, to a disable time an internal idle signal; and an internal command signal generation block configured to generate an internal write signal if it is determined that a combination of counting signals counted during an enable period of the control signal is a first combination and generate an internal precharge signal if it is determined that the combination of the counting signals is a second combination.

Abstract: A semiconductor memory device includes an internal signal generation block configured to generate a control signal which is enabled from a generation time of an internal active signal enabled if it is determined that a combination of external commands in synchronization with a rising edge of an external clock inputted from an outside is a preset combination, to a disable time an internal idle signal; and an internal command signal generation block configured to generate an internal write signal if it is determined that a combination of counting signals counted during an enable period of the control signal is a first combination and generate an internal precharge signal if it is determined that the combination of the counting signals is a second combination.

Abstract: A multi-bit test circuit for a semiconductor memory is configured to cause an active command to activate active signals. At least two active signals are respectively inputted to a plurality of banks at different timings in a multi-bit test mode.

Abstract: A semiconductor memory apparatus includes: an address buffer configured to buffer an input address and generate a buffered address; a command buffer configured to buffer a chip selection command and generate a buffered command; a latch control unit configured to receive an internal clock and the buffered command and generate a latch control signal; and an address latch unit configured to latch the buffered address based on the latch control signal.

Abstract: A multi-bit test circuit for a semiconductor memory is configured to cause an active command to activate active signals. At least two active signals are respectively inputted to a plurality of banks at different timings in a multi-bit test mode.

Abstract: A semiconductor memory apparatus includes: an address buffer configured to buffer an input address and generate a buffered address; a command buffer configured to buffer a chip selection command and generate a buffered command; a latch control unit configured to receive an internal clock and the buffered command and generate a latch control signal; and an address latch unit configured to latch the buffered address based on the latch control signal.

Abstract: An address latch circuit of a semiconductor memory device is provided. The address latch circuit includes a first address latch part, which latches a first address signal fed from outside according to a first address latch signal and outputs a second address signal. An address shift part shifts the second address signal according to a divided clock, which is divided from an external clock, and a write latency signal, and outputs a third address signal. A second address latch part latches the third address signal according to a second address latch signal and outputs a fourth address signal.

Abstract: A command decoder circuit generates command signals for performing internal operations and according to external command signals, according to values of the write latency values and whether write latency is an even numbered or odd-numbered value.

Abstract: The present invention relates to a semiconductor memory device having a clock buffer circuit which buffers an external clock to generate an internal clock, wherein the clock buffer circuit comprises a rising clock buffer which buffers an external clock to generate a rising internal clock corresponding to a rising edge of the external clock; and a falling clock buffer which buffers the external clock to generate a falling internal clock corresponding to a falling edge of the external clock, whereby the external signal is input to the internal circuit in synchronization with the rising internal clock and the falling internal clock.

Abstract: An apparatus includes a control unit for generating an input control signal to select a global input/output line to which data is transmitted. A repeater receives data from the global input/output line to output the data to a global input/output line corresponding to the input control signal. A plurality of input drivers receive the data from the repeater to transmit the data to a local input/output line connected to each memory bank.

Abstract: An address latch circuit of a semiconductor memory device is provided. The address latch circuit includes a first address latch part, which latches a first address signal fed from outside according to a first address latch signal and outputs a second address signal. An address shift part shifts the second address signal according to a divided clock, which is divided from an external clock, and a write latency signal, and outputs a third address signal. A second address latch part latches the third address signal according to a second address latch signal and outputs a fourth address signal.

Abstract: A charge pump circuit includes a test mode control unit for generating a plurality of control signals according to a test mode enable signal and an input signal and fixing one of the plurality of the control signals depending upon whether a fuse has been cut or not, a ring oscillator for outputting an output frequency of which varies according to an output of the test mode control unit, and a charge pump for generating a high voltage, which is higher than an external voltage, according to an output of the ring oscillator.

Abstract: A charge pump circuit comprises a decoder for generating a plurality of control signals, a ring oscillator an output frequency of which varies according to the plurality of the control signals, a charge pump for generating a high voltage, which is higher than an external voltage, according to an output of the ring oscillator, and a fuse tuning unit for fixing one of the plurality of the control signals.

Abstract: A command decoder is provided for controlling internal circuits of a semiconductor chip to operate in synchronism with a first internal clock signal having a pulse width, which is twice as wide as that of an external clock signal, and a second internal clock signal having an opposite phase to the first internal clock signal. An internal operation controller controls internal circuits of a semiconductor chip to operate in synchronism with a first internal clock signal having a pulse width, which is N times as wide as that of an external clock signal, if the command signal is received at a first rising edge of the external clock signal, and controls the internal circuits of the semiconductor chip to operate in synchronism with a second internal clock signal having an opposite phase to the first internal clock signal, if the command signal is received at a second rising edge of the external clock signal.

Abstract: A command decoder is provided for controlling internal circuits of a semiconductor chip to operate in synchronism with a first internal clock signal having a pulse width, which is twice as wide as that of an external clock signal, and a second internal clock signal having an opposite phase to the first internal clock signal. An internal operation controller controls internal circuits of a semiconductor chip to operate in synchronism with a first internal clock signal having a pulse width, which is N times as wide as that of an external clock signal, if the command signal is received at a first rising edge of the external clock signal, and controls the internal circuits of the semiconductor chip to operate in synchronism with a second internal clock signal having an opposite phase to the first internal clock signal, if the command signal is received at a second rising edge of the external clock signal.

Abstract: Provided is directed to a delay locked loop control circuit capable of reducing a test time and preventing a yield from being reduced, by preventing a failure due to a charge sharing and a failure in a specific frequency and voltage due to a noise of a feedback clock, by means of including: a level setting unit for setting an initial level of a locked state signal, which is decided whether or not phases of a reference clock and a feedback clock are aligned; a signal generation unit for generating a third control signal according to a first control signal comparing phases of the reference clock and the feedback clock, and a second control signal checking out phases of the reference clock and the feedback clock in every predetermined time; a level maintaining unit for maintaining a level of the locked state signal according to the locked state signal and a fourth control signal comparing a signal delaying the feedback clock for a predetermined time with the reference clock; a detection unit for varying a level

Abstract: An input buffer of a semiconductor memory device includes a first buffer block for buffering an input data through a delay path selected from a plurality of delay paths, and a second buffer block for buffering an input data strobe signal through a delay path selected from a plurality of delay paths, wherein the plurality of delay paths of the first buffer block and the plurality of delay paths of the second buffer block are identically formed by the same devices, and the corresponding delay paths are selected from the plurality of delay paths according to the same selecting signals. Although the input buffer fails to obtain a margin of a data setup and hold time in an input/output sense amplifier due to variations of the data setup and hold time by maximum and minimum values of tDQSS in a write operation mode, the input buffer can easily obtain the margin of the data setup and hold time in response to a special test mode signal.

Abstract: An input buffer of a semiconductor memory device includes a first buffer block for buffering an input data through a delay path selected from a plurality of delay paths, and a second buffer block for buffering an input data strobe signal through a delay path selected from a plurality of delay paths, wherein the plurality of delay paths of the first buffer block and the plurality of delay paths of the second buffer block are identically formed by the same devices, and the corresponding delay paths are selected from the plurality of delay paths according to the same selecting signals. Although the input buffer fails to obtain a margin of a data setup and hold time in an input/output sense amplifier due to variations of the data setup and hold time by maximum and minimum values of tDQSS in a write operation mode, the input buffer can easily obtain the margin of the data setup and hold time in response to a special test mode signal.