Abstract: A vehicle seat reinforcement device includes a leg portion mounted on a floor panel, a seat cushion frame slidably mounted on the leg portion, and a load reinforcing structure connected between the leg portion and the seat cushion frame, wherein when a seat belt anchorage load is transferred to the seat cushion frame, the seat cushion frame is locked to the leg portion by the load reinforcing structure.

Abstract: A delay adjusting apparatus may include at least one selective delay element electrically coupled to an electrical path between an input terminal and an output terminal of the electrical path, and the at least one selective delay element configured to add a delay factor to the electrical path in response to an enable signal. The delay adjusting apparatus may include at least one fuse circuit configured to control electrical coupling of an e-fuse, in response to a program signal, and program the enable signal.

Abstract: A delay adjusting apparatus may include at least one selective delay element electrically coupled to an electrical path between an input terminal and an output terminal of the electrical path, and the at least one selective delay element configured to add a delay factor to the electrical path in response to an enable signal. The delay adjusting apparatus may include at least one fuse circuit configured to control electrical coupling of an e-fuse, in response to a program signal, and program the enable signal.

Abstract: A semiconductor memory device includes an internal signal generation block configured to generate a control signal which is enabled from a generation time of an internal active signal enabled if it is determined that a combination of external commands in synchronization with a rising edge of an external clock inputted from an outside is a preset combination, to a disable time an internal idle signal; and an internal command signal generation block configured to generate an internal write signal if it is determined that a combination of counting signals counted during an enable period of the control signal is a first combination and generate an internal precharge signal if it is determined that the combination of the counting signals is a second combination.

Abstract: A clock transfer circuit includes a clock transfer unit configured to receive an external clock and transfer the received external clock as one or more internal clocks and a clock control unit configured to control the clock transfer unit to transfer the external clock as a column clock among the internal clocks in response to an active command and block a transfer of the external clock as the column clock in response to a precharge command.

Abstract: A semiconductor memory device includes an internal signal generation block configured to generate a control signal which is enabled from a generation time of an internal active signal enabled if it is determined that a combination of external commands in synchronization with a rising edge of an external clock inputted from an outside is a preset combination, to a disable time an internal idle signal; and an internal command signal generation block configured to generate an internal write signal if it is determined that a combination of counting signals counted during an enable period of the control signal is a first combination and generate an internal precharge signal if it is determined that the combination of the counting signals is a second combination.

Abstract: A semiconductor device includes an internal operation signal generation circuit configured to generate an internal operation signal in response to a signal applied through a reset signal input pad during a test period.

Abstract: A clock transfer circuit includes a clock transfer unit configured to receive an external clock and transfer the received external clock as one or more internal clocks and a clock control unit configured to control the clock transfer unit to transfer the external clock as a column clock among the internal clocks in response to an active command and block a transfer of the external clock as the column clock in response to a precharge command.

Abstract: A multi-bit test circuit for a semiconductor memory is configured to cause an active command to activate active signals. At least two active signals are respectively inputted to a plurality of banks at different timings in a multi-bit test mode.

Abstract: A semiconductor memory apparatus includes: an address buffer configured to buffer an input address and generate a buffered address; a command buffer configured to buffer a chip selection command and generate a buffered command; a latch control unit configured to receive an internal clock and the buffered command and generate a latch control signal; and an address latch unit configured to latch the buffered address based on the latch control signal.

Abstract: A multi-bit test circuit for a semiconductor memory is configured to cause an active command to activate active signals. At least two active signals are respectively inputted to a plurality of banks at different timings in a multi-bit test mode.

Abstract: A semiconductor device includes an internal operation signal generation circuit configured to generate an internal operation signal in response to a signal applied through a reset signal input pad during a test period.

Abstract: A semiconductor memory device is capable of transferring address signals at high speed and improving the operation reliability even though an input rate of an address signal increases, and thus a degradation of an operation speed caused by applying a bus inversion scheme can be prevented and power consumption can be reduced. The semiconductor memory device includes a bus inversion decoding block configured to determine whether a plurality of address signals are inverted or not by decoding an indication control signal, and an address buffer block configured to receive two address signals per one cycle of an external clock, align the received address signals for parallel processing, and transfer the address signals or inverted address signals according to an output of the bus inversion decoding block.

Abstract: A buffer control circuit of a memory device has an auto-refresh buffer controller configured to detect a data training operation in an auto-refresh mode and a controller configured to enable an input buffer in response to an enable signal generated in the data training operation by the auto-refresh buffer controller.

Abstract: A semiconductor memory device is capable of securing margins of setup/hold times for receiving addresses. The device includes an address buffering unit, a data input/output line, a selecting unit and an output circuit. The address buffering unit buffers input addresses. The data input/output line transfers data with a cell array. The selecting unit selectively outputs the buffered addresses transferred from the address buffering unit and the data transferred through the data input/output line according to modes of the device. The output circuit latches an output of the selecting unit to be outputted from the device.

Abstract: A semiconductor memory device includes a plurality of address pads, a plurality of data pads, a mode entry controlling unit configured to control the entry to a data masking mode in response to a write command signal and signals inputted through predetermined pads among the plurality of address pads, a signal classifying unit configured to classify signals inputted sequentially and in parallel through the plurality of address pads into column address signals and data masking signals in response to an output signal of the mode entry controlling unit and a write latency signal, and a pad masking signal generating unit configured to generate pad masking signals to control the masking of data inputted through the plurality of data pads, where the pad masking signals are generated by converting the data masking signals in response to the output signal of the mode entry controlling unit.

Abstract: Buffer control circuit of memory device having a buffer control circuit of a memory device comprises an auto-refresh buffer controller configured to detect a data training operation in an auto-refresh mode and a controller configured to enable an input buffer in response to an enable signal generated in the data training operation by the auto-refresh buffer controller.

Abstract: A semiconductor memory apparatus includes: an address buffer configured to buffer an input address and generate a buffered address; a command buffer configured to buffer a chip selection command and generate a buffered command; a latch control unit configured to receive an internal clock and the buffered command and generate a latch control signal; and an address latch unit configured to latch the buffered address based on the latch control signal.

Abstract: A semiconductor memory device is capable of transferring address signals at high speed and improving the operation reliability even though an input rate of an address signal increases, and thus a degradation of an operation speed caused by applying a bus inversion scheme can be prevented and power consumption can be reduced. The semiconductor memory device includes a bus inversion decoding block configured to determine whether a plurality of address signals are inverted or not by decoding an indication control signal, and an address buffer block configured to receive two address signals per one cycle of an external clock, align the received address signals for parallel processing, and transfer the address signals or inverted address signals according to an output of the bus inversion decoding block.

Abstract: Buffer control circuit of memory device having a buffer control circuit of a memory device comprises an auto-refresh buffer controller configured to detect a data training operation in an auto-refresh mode and a controller configured to enable an input buffer in response to an enable signal generated in the data training operation by the auto-refresh buffer controller.