Patents by Inventor Sun-Won Kang
Sun-Won Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240140368Abstract: Provided are a vehicle sensor cleaning apparatus and a control method thereof. The vehicle sensor cleaning apparatus includes a liquid sprayer configured to spray washer fluid on at least one sensor arranged in a vehicle, an air sprayer configured to spray air on the at least one sensor, a liquid controller configured to control washer fluid spraying of the liquid sprayer, and an air controller configured to control air spraying of the air sprayer.Type: ApplicationFiled: October 25, 2023Publication date: May 2, 2024Applicants: DY AUTO Corporation, DY-ESSYS Corp.Inventors: Jong Wook Lee, Sin Won Kang, Seong Jun Kim, Kyung Seon Min, Gyu Seon Lee, Jong Hyun Jin, Min Wook Park, Je Min Mun, Sun Ju Kim, Ki Chan Lee
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Patent number: 10784216Abstract: Provided are a semiconductor device and a semiconductor package including the same. The semiconductor device comprises a semiconductor chip body including a first chip pad on a top surface, a passivation film disposed on the semiconductor chip body and a first redistribution layer that is disposed between the passivation film and the semiconductor chip body with an opening to expose a first chip center pad region at least partially overlapping the first chip pad, a first redistribution center pad region connected to the first chip center pad region, and a first edge pad region spaced apart from the first redistribution center pad region, through the passivation film, wherein a top surface of the first chip center pad region and a top surface of the first redistribution center pad region are not disposed on the same plane.Type: GrantFiled: April 24, 2019Date of Patent: September 22, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Young Kim, Sun-Won Kang, Jin-Chan Ahn
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Patent number: 10756062Abstract: A semiconductor chip includes a semiconductor substrate, a through electrode, an inter-mediation pad, an upper pad, and a rewiring line. The semiconductor substrate includes a first surface that is an active surface and a second surface that is opposite to the first surface. The through electrode penetrates the semiconductor substrate and is disposed in at least one column in a first direction in a center portion of the semiconductor substrate. The inter-mediation pad is disposed in at least one column in the first direction in an edge portion of the second surface. The upper pad is disposed on the second surface and connected to the through electrode. The rewiring line is disposed on the second surface and connects the inter-mediation pad to the upper pad.Type: GrantFiled: March 20, 2019Date of Patent: August 25, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung-Soo Kim, Seung-Duk Baek, Sun-Won Kang, Ho-Geon Song, Gun-Ho Chang
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Patent number: 10679956Abstract: A semiconductor memory chip includes an upper data pad region, a lower data pad region, and an additional pad region. Upper data pads, upper data strobe signal pair pads, and an upper data mask signal pad are arranged in the upper data pad region. Lower data pads, lower data strobe signal pair pads, and a lower data mask signal pad are arranged in the lower data pad region adjacent to and below the upper data pad region. An inverted termination data strobe signal pad used for a second semiconductor memory package and internally connected to the upper data mask signal pad, which is used for a first semiconductor memory package, is arranged in the additional pad region adjacent to and above the upper data pad region.Type: GrantFiled: March 11, 2019Date of Patent: June 9, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung Soo Kim, Won Young Kim, Sun Won Kang
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Publication number: 20200013753Abstract: A semiconductor chip includes a semiconductor substrate, a through electrode, an inter-mediation pad, an upper pad, and a rewiring line. The semiconductor substrate includes a first surface that is an active surface and a second surface that is opposite to the first surface. The through electrode penetrates the semiconductor substrate and is disposed in at least one column in a first direction in a center portion of the semiconductor substrate. The inter-mediation pad is disposed in at least one column in the first direction in an edge portion of the second surface. The upper pad is disposed on the second surface and connected to the through electrode. The rewiring line is disposed on the second surface and connects the inter-mediation pad to the upper pad.Type: ApplicationFiled: March 20, 2019Publication date: January 9, 2020Inventors: Kyoung-Soo Kim, Seung-Duk Baek, Sun-Won Kang, Ho-Geon Song, Gun-Ho Chang
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Publication number: 20190252332Abstract: Provided are a semiconductor device and a semiconductor package including the same. The semiconductor device comprises a semiconductor chip body including a first chip pad on a top surface, a passivation film disposed on the semiconductor chip body and a first redistribution layer that is disposed between the passivation film and the semiconductor chip body with an opening to expose a first chip center pad region at least partially overlapping the first chip pad, a first redistribution center pad region connected to the first chip center pad region, and a first edge pad region spaced apart from the first redistribution center pad region, through the passivation film, wherein a top surface of the first chip center pad region and a top surface of the first redistribution center pad region are not disposed on the same plane.Type: ApplicationFiled: April 24, 2019Publication date: August 15, 2019Inventors: Won-Young Kim, Sun-Won Kang, Jin-Chan Ahn
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Publication number: 20190206819Abstract: A semiconductor memory chip includes an upper data pad region, a lower data pad region, and an additional pad region. Upper data pads, upper data strobe signal pair pads, and an upper data mask signal pad are arranged in the upper data pad region. Lower data pads, lower data strobe signal pair pads, and a lower data mask signal pad are arranged in the lower data pad region adjacent to and below the upper data pad region. An inverted termination data strobe signal pad used for a second semiconductor memory package and internally connected to the upper data mask signal pad, which is used for a first semiconductor memory package, is arranged in the additional pad region adjacent to and above the upper data pad region.Type: ApplicationFiled: March 11, 2019Publication date: July 4, 2019Inventors: KYOUNG SOO KIM, Won Young Kim, Sun Won Kang
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Patent number: 10297559Abstract: Provided are a semiconductor device and a semiconductor package including the same. The semiconductor device comprises a semiconductor chip body including a first chip pad on a top surface, a passivation film disposed on the semiconductor chip body and a first redistribution layer that is disposed between the passivation film and the semiconductor chip body with an opening to expose a first chip center pad region at least partially overlapping the first chip pad, a first redistribution center pad region connected to the first chip center pad region, and a first edge pad region spaced apart from the first redistribution center pad region, through the passivation film, wherein a top surface of the first chip center pad region and a top surface of the first redistribution center pad region are not disposed on the same plane.Type: GrantFiled: October 17, 2016Date of Patent: May 21, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Young Kim, Sun-Won Kang, Jin-Chan Ahn
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Patent number: 10269740Abstract: A semiconductor memory chip includes an upper data pad region, a lower data pad region, and an additional pad region. Upper data pads, upper data strobe signal pair pads, and an upper data mask signal pad are arranged in the upper data pad region. Lower data pads, lower data strobe signal pair pads, and a lower data mask signal pad are arranged in the lower data pad region adjacent to and below the upper data pad region. An inverted termination data strobe signal pad used for a second semiconductor memory package and internally connected to the upper data mask signal pad, which is used for a first semiconductor memory package, is arranged in the additional pad region adjacent to and above the upper data pad region.Type: GrantFiled: December 19, 2017Date of Patent: April 23, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoung Soo Kim, Won Young Kim, Sun Won Kang
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Patent number: 10141293Abstract: A semiconductor package includes a package base substrate including bonding pads and a connection pads respectively on an upper surface and a lower surface of the package base substrate, four semiconductor chips attached onto the package base substrate, including a 1A semiconductor chip, a 1B semiconductor chip, a 2A semiconductor chip, and a 2B semiconductor chip, and each including a plurality of chip pads that are adjacent to a first edge of an upper surface of each of the 1A semiconductor chip, the 1B semiconductor chip, the 2A semiconductor chip, and the 2B semiconductor chip, and a bonding wire electrically connecting the chip pad and the bonding pad to each other, wherein the four semiconductor chips are disposed on the package base substrate such that first edges of the four semiconductor chips respectively face edges of the package base substrate that are different from each other.Type: GrantFiled: December 29, 2017Date of Patent: November 27, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Seok-hong Kwon, Sang-nam Jeong, Sun-won Kang, Hee-jin Lee
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Publication number: 20180337151Abstract: A semiconductor memory chip includes an upper data pad region, a lower data pad region, and an additional pad region. Upper data pads, upper data strobe signal pair pads, and an upper data mask signal pad are arranged in the upper data pad region. Lower data pads, lower data strobe signal pair pads, and a lower data mask signal pad are arranged in the lower data pad region adjacent to and below the upper data pad region. An inverted termination data strobe signal pad used for a second semiconductor memory package and internally connected to the upper data mask signal pad, which is used for a first semiconductor memory package, is arranged in the additional pad region adjacent to and above the upper data pad region.Type: ApplicationFiled: December 19, 2017Publication date: November 22, 2018Inventors: KYOUNG SOO KIM, Won Young Kim, Sun Won Kang
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Patent number: 10134713Abstract: A semiconductor package includes a printed circuit board, a resistor circuit, and first and second semiconductor chips. First and second pads are on a first surface of the printed circuit board, and external connection terminal is on a second surface of the printed circuit board. The resistor circuit has a first connection terminal connected to the first pad and a second connection terminal connected to the second pad. The first semiconductor chip is connected to the first pad and the second semiconductor chip is stacked on the first semiconductor chip and connected to the second pad. The printed circuit board includes a signal transfer line connecting a branch in the printed circuit board to the external connection terminal. A first transfer line connects the branch to the first pad. A second transfer line connects the branch to the second pad.Type: GrantFiled: November 16, 2017Date of Patent: November 20, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang-seok Kim, Sun-won Kang, Il-joon Kim
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Publication number: 20180145054Abstract: A semiconductor package includes a printed circuit board, a resistor circuit, and first and second semiconductor chips. First and second pads are on a first surface of the printed circuit board, and external connection terminal is on a second surface of the printed circuit board. The resistor circuit has a first connection terminal connected to the first pad and a second connection terminal connected to the second pad. The first semiconductor chip is connected to the first pad and the second semiconductor chip is stacked on the first semiconductor chip and connected to the second pad. The printed circuit board includes a signal transfer line connecting a branch in the printed circuit board to the external connection terminal. A first transfer line connects the branch to the first pad. A second transfer line connects the branch to the second pad.Type: ApplicationFiled: November 16, 2017Publication date: May 24, 2018Inventors: Kwang-seok KIM, Sun-won KANG, IL-joon KIM
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Publication number: 20180122790Abstract: A semiconductor package includes a package base substrate including bonding pads and a connection pads respectively on an upper surface and a lower surface of the package base substrate, four semiconductor chips attached onto the package base substrate, including a 1A semiconductor chip, a 1B semiconductor chip, a 2A semiconductor chip, and a 2B semiconductor chip, and each including a plurality of chip pads that are adjacent to a first edge of an upper surface of each of the 1A semiconductor chip, the 1B semiconductor chip, the 2A semiconductor chip, and the 2B semiconductor chip, and a bonding wire electrically connecting the chip pad and the bonding pad to each other, wherein the four semiconductor chips are disposed on the package base substrate such that first edges of the four semiconductor chips respectively face edges of the package base substrate that are different from each other.Type: ApplicationFiled: December 29, 2017Publication date: May 3, 2018Inventors: Seok-hong KWON, Sang-nam JEONG, Sun-won KANG, Hee-jin LEE
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Patent number: 9859263Abstract: A semiconductor package includes a package base substrate including bonding pads and a connection pads respectively on an upper surface and a lower surface of the package base substrate, four semiconductor chips attached onto the package base substrate, including a 1A semiconductor chip, a 1B semiconductor chip, a 2A semiconductor chip, and a 2B semiconductor chip, and each including a plurality of chip pads that are adjacent to a first edge of an upper surface of each of the 1A semiconductor chip, the 1B semiconductor chip, the 2A semiconductor chip, and the 2B semiconductor chip, and a bonding wire electrically connecting the chip pad and the bonding pad to each other, wherein the four semiconductor chips are disposed on the package base substrate such that first edges of the four semiconductor chips respectively face edges of the package base substrate that are different from each other.Type: GrantFiled: August 17, 2016Date of Patent: January 2, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Seok-hong Kwon, Sang-nam Jeong, Sun-won Kang, Hee-jin Lee
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Patent number: 9780049Abstract: A semiconductor package includes a substrate; and first and second semiconductor chips sequentially disposed on the substrate so that active surfaces of the first and second semiconductor chips face each other, wherein the first and second semiconductor chips are center pad-type semiconductor chips each having I/O pads arranged in two columns to be adjacent to a central line thereof, and I/O pads of the second semiconductor chip are electrically connected directly to the substrate without intersecting the central line of the second semiconductor chip.Type: GrantFiled: May 15, 2014Date of Patent: October 3, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin-chan Ahn, Sun-won Kang
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Publication number: 20170133333Abstract: Provided are a semiconductor device and a semiconductor package including the same. The semiconductor device comprises a semiconductor chip body including a first chip pad on a top surface, a passivation film disposed on the semiconductor chip body and a first redistribution layer that is disposed between the passivation film and the semiconductor chip body with an opening to expose a first chip center pad region at least partially overlapping the first chip pad, a first redistribution center pad region connected to the first chip center pad region, and a first edge pad region spaced apart from the first redistribution center pad region, through the passivation film, wherein a top surface of the first chip center pad region and a top surface of the first redistribution center pad region are not disposed on the same plane.Type: ApplicationFiled: October 17, 2016Publication date: May 11, 2017Inventors: Won-Young Kim, Sun-Won Kang, Jin-Chan Ahn
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Publication number: 20170125393Abstract: A semiconductor package includes a package base substrate including bonding pads and a connection pads respectively on an upper surface and a lower surface of the package base substrate, four semiconductor chips attached onto the package base substrate, including a 1A semiconductor chip, a 1B semiconductor chip, a 2A semiconductor chip, and a 2B semiconductor chip, and each including a plurality of chip pads that are adjacent to a first edge of an upper surface of each of the 1A semiconductor chip, the 1B semiconductor chip, the 2A semiconductor chip, and the 2B semiconductor chip, and a bonding wire electrically connecting the chip pad and the bonding pad to each other, wherein the four semiconductor chips are disposed on the package base substrate such that first edges of the four semiconductor chips respectively face edges of the package base substrate that are different from each other.Type: ApplicationFiled: August 17, 2016Publication date: May 4, 2017Inventors: Seok-hong KWON, Sang-nam JEONG, Sun-won KANG, Hee-jin LEE
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Patent number: 9355947Abstract: A printed circuit board (PCB) includes a base substrate including upper and lower surfaces, a plurality of solder ball pads separately formed on the lower surface of the base substrate in a radial direction and forming one or more radial pad groups, a plurality of first traces respectively connected to the plurality of solder ball pads and extending to an inside of the radial pad group, and a plurality of second traces respectively connected to the plurality of first traces and extending to an outside of the radial pad group.Type: GrantFiled: April 28, 2015Date of Patent: May 31, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyo-soon Kang, Sun-won Kang, Joon-young Park, Doo-hee Hwang, Tae-young Yoon
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Publication number: 20150332993Abstract: A printed circuit board (PCB) includes a base substrate including upper and lower surfaces, a plurality of solder ball pads separately formed on the lower surface of the base substrate in a radial direction and forming one or more radial pad groups, a plurality of first traces respectively connected to the plurality of solder ball pads and extending to an inside of the radial pad group, and a plurality of second traces respectively connected to the plurality of first traces and extending to an outside of the radial pad group.Type: ApplicationFiled: April 28, 2015Publication date: November 19, 2015Inventors: Hyo-soon KANG, Sun-won KANG, Joon-young PARK, Doo-hee HWANG, Tae-young YOON