Abstract: The present invention relates to: a method for preparing a non-oxidized carbon nanotube dispersion through mechanical impregnation so as to apply carbon nanotubes having a hydrophobic surface and a bundle shape as a high-performance conductive material of a negative electrode or a positive electrode for a secondary battery through solvent dispersion without acid treatment; and a non-oxidized carbon nanotube dispersion for a conductive material of a secondary battery, prepared by the method.

Abstract: A data processing system includes data processing devices each including a computing memory and configured to perform a task; one or more host devices connected to the data processing devices, and each configured to: select one or more of the data processing devices based on meta information including a size of a memory, and sizes of the computing memories of the respective data processing devices, and request the selected processing devices to perform a first task; a network switch configured to connect the one or more host devices to the data processing devices; and a network manager in the network switch and configured to: collect free memories of the respective data processing devices based on the meta information and the sizes of the computing memories of the respective data processing devices, and control the one or more host devices to use some of the free memories.

Abstract: A battery module includes a plurality of overlapped battery cells and an insert panel inserted between the overlapped battery cells. The battery module further includes a top flange extended in an overlapping direction of the battery cells above the battery cells.

Abstract: A memory system includes at least one memory device. The at least one memory device includes a plurality of memory areas. The memory system includes a device allocation manager and security erase circuitry. The device allocation manager determines which of the plurality of memory areas is allocated or released based on a request input from at least one host. The security erase circuitry stores a security erase task for a first memory area, which is associated with a release determined by the device allocation manager, in an erase job queue, and removes the security erase task from the erase job queue when the first memory area is reallocated to a first host to which the first memory area was allocated before the release.

Abstract: A display device includes: a light source unit including a plurality of light sources; a cover bottom including a horizontal surface on which the plurality of light sources are seated, and a side surface bent along an edge of the horizontal surface; an optical unit on the light source unit; a display panel on the optical unit; a first module film being transparent, supporting a back surface of the optical unit, and including a first edge portion attached to and fixed to an outer side of the side surface of the cover bottom; and a second module film being transparent, attached to a back surface of the display panel, and including a second edge portion attached to and fixed to an outer side of the edge portion.

Abstract: A display device includes a first display panel realizing a first image light of a first resolution; and a second display panel realizing a second image light synchronized with the first image light, the second image light having a second resolution lower than the first resolution, wherein a second virtual image implemented by the second image light is superimposed with a first virtual image implemented by the first image light to implement a virtual reality image.

Abstract: A data processing system includes data processing devices each including a computing memory and configured to perform a task; one or more host devices connected to the data processing devices, and each configured to: select one or more of the data processing devices based on meta information including a size of a memory, and sizes of the computing memories of the respective data processing devices, and request the selected processing devices to perform a first task; a network switch configured to connect the one or more host devices to the data processing devices; and a network manager in the network switch and configured to: collect free memories of the respective data processing devices based on the meta information and the sizes of the computing memories of the respective data processing devices, and control the one or more host devices to use some of the free memories.

Abstract: A display device includes: a light source unit including a plurality of light sources; a cover bottom including a horizontal surface on which the plurality of light sources are seated, and a side surface bent along an edge of the horizontal surface; an optical unit on the light source unit; a display panel on the optical unit; a first module film being transparent, supporting a back surface of the optical unit, and including a first edge portion attached to and fixed to an outer side of the side surface of the cover bottom; and a second module film being transparent, attached to a back surface of the display panel, and including a second edge portion attached to and fixed to an outer side of the edge portion.

Abstract: A display device includes a display panel and a cover window including a density control area and being located corresponding to a transmission direction of a light emitted from the display panel, a refractive index of the density control area being gradually changed, wherein the refractive index of the density control area is gradually changed through voids.

Abstract: A memory system is disclosed, which relates to technology for implementing data communication between memory devices. The memory system includes a plurality of memory devices and a memory controller. The memory devices allow a data packet composed of data and header information to be directly communicated between the memory devices. The memory controller transmits the data packet to a source memory device from among the plurality of memory devices, and receives the data packet from a last memory device from among the plurality of memory devices. Each of the memory devices hashes the header information such that the data is accessed, using a result of the hash, in address regions located at different positions.

Abstract: A memory system is disclosed, which relates to technology for implementing data communication between memory devices. The memory system includes a plurality of memory devices and a memory controller. The memory devices allow a data packet composed of data and header information to be directly communicated between the memory devices. The memory controller transmits the data packet to a source memory device from among the plurality of memory devices, and receives the data packet from a last memory device from among the plurality of memory devices. Each of the memory devices hashes the header information such that the data is accessed, using a result of the hash, in address regions located at different positions.

Abstract: A memory system may include: a plurality of memory devices each including a user area and an over-provisioning area (OP area); and a controller configured for controlling the plurality of memory devices, wherein the controller includes: a detection circuit configured for detecting a defective memory device among the plurality of memory devices; a selection circuit configured for selecting an available memory device excluding the defective memory device among the plurality of memory devices; and a processor configured for moving target data stored in the defective memory device into the OP area of the available memory device.

Abstract: A polyhedron type display device includes: a plurality of liquid crystal panels connected to each other to constitute a polyhedral shape; a light source housing at a center of mass of the polyhedral shape; a light source unit accommodated in the light source housing, the light source unit emitting a light to supply the light to the plurality of liquid crystal panels; a light source supporting pillar connecting and supporting the light source housing and the plurality of liquid crystal panels; a structure supporting pedestal supporting the light source supporting pillar; a supporting panel supporting the plurality of liquid crystal panels; a radiating pillar connected to the light source unit and emitting a heat of the light source unit; and a protecting cover covering and protecting the radiating pillar.

Abstract: A memory system is disclosed, which relates to technology for implementing data communication between memory devices. The memory system includes a plurality of memory devices and a memory controller. The memory devices allow a data packet composed of data and header information to be directly communicated between the memory devices. The memory controller transmits the data packet to a source memory device from among the plurality of memory devices, and receives the data packet from a last memory device from among the plurality of memory devices. Each of the memory devices hashes the header information such that the data is accessed, using a result of the hash, in address regions located at different positions.

Abstract: A multilayer ceramic electronic component includes: a ceramic body having a hexahedral shape including at least one rounded corner and including dielectric layers and first and second internal electrodes, and first and second external electrodes. The first and second external electrodes respectively include first and second base electrode layers which at least partially contact the first and second external sides of the ceramic body, and first and second plating layers disposed to cover the first and second base electrode layers, respectively. CP/CT is equal to or greater than 1.6 and equal to or less than 2.4, where CP is a length of a rounded boundary line of the rounded corner of the ceramic body viewed in a cross-section in length and thickness directions, and CT is a thickness of one of the first and second base electrode layers at a central point in the thickness direction.

Abstract: A memory system is disclosed, which relates to technology for an accelerator of a high-capacity memory device. The memory system includes a plurality of memories configured to store data therein, and a pooled memory controller (PMC) configured to perform map computation by reading the data stored in the plurality of memories and storing resultant data produced by the map computation in the plurality of memories.

Abstract: A multilayer ceramic electronic component includes: a ceramic body including a dielectric layer and a first internal electrode and a second internal electrode disposed in a stacking direction to face each other with the dielectric layer interposed therebetween; and a first external electrode electrically connected to the first internal electrode and a second external electrode electrically connected to the second internal electrode. Where a length of the first electrode layer in a length direction of the ceramic body is denoted by A and a length of the second electrode layer in a length direction of the ceramic body is denoted by B, B is shorter than A.

Abstract: A memory system is disclosed, which relates to technology for an accelerator of a high-capacity memory device. The memory system includes a plurality of memories configured to store data therein, and a pooled memory controller (PMC) configured to perform map computation by reading the data stored in the plurality of memories and storing resultant data produced by the map computation in the plurality of memories.

Abstract: A memory system is disclosed, which relates to technology for implementing data communication between memory devices. The memory system includes a plurality of memory devices and a memory controller. The memory devices allow a data packet composed of data and header information to be directly communicated between the memory devices. The memory controller transmits the data packet to a source memory device from among the plurality of memory devices, and receives the data packet from a last memory device from among the plurality of memory devices. Each of the memory devices hashes the header information such that the data is accessed, using a result of the hash, in address regions located at different positions.

Abstract: A multilayer ceramic electronic component includes: a ceramic body having a hexahedral shape including at least one rounded corner and including dielectric layers and first and second internal electrodes, and first and second external electrodes. The first and second external electrodes respectively include first and second base electrode layers which at least partially contact the first and second external sides of the ceramic body, and first and second plating layers disposed to cover the first and second base electrode layers, respectively. CP/CT is equal to or greater than 1.6 and equal to or less than 2.4, where CP is a length of a rounded boundary line of the rounded corner of the ceramic body viewed in a cross-section in length and thickness directions, and CT is a thickness of one of the first and second base electrode layers at a central point in the thickness direction.