Abstract: A vehicle seat reinforcement device includes a leg portion mounted on a floor panel, a seat cushion frame slidably mounted on the leg portion, and a load reinforcing structure connected between the leg portion and the seat cushion frame, wherein when a seat belt anchorage load is transferred to the seat cushion frame, the seat cushion frame is locked to the leg portion by the load reinforcing structure.

Abstract: The present specification relates to a conductive structure body, a method for manufacturing the same, and an electrode and an electronic device including the conductive structure body.

Abstract: A mold for producing a hydrogel support for a 3-dimensional (3D) cell culture, includes: an upper mold comprising a base and a plurality of upper unit molds protruding downward from the base to form accommodating portions of a female type corresponding to shapes of hydrogel supports, having through holes at bottoms thereof, and patterned at a lower portion of the base; a lower mold where a plurality of lower unit molds are patterned, the plurality of lower unit molds formed in a female type to respectively accommodate the plurality of upper unit molds protruding downward and having sealed lower portions; and an ejecting unit for separating, from the accommodating portions of the plurality of upper unit molds, the hydrogel supports that are coagulated after being inserted into the through holes respectively formed in the plurality of upper unit molds.

Abstract: A mold for producing a hydrogel support for a 3-dimensional (3D) cell culture, includes: an upper mold comprising a base and a plurality of upper unit molds protruding downward from the base to form accommodating portions of a female type corresponding to shapes of hydrogel supports, having through holes at bottoms thereof, and patterned at a lower portion of the base; a lower mold where a plurality of lower unit molds are patterned, the plurality of lower unit molds formed in a female type to respectively accommodate the plurality of upper unit molds protruding downward and having sealed lower portions; and an ejecting unit for separating, from the accommodating portions of the plurality of upper unit molds, the hydrogel supports that are coagulated after being inserted into the through holes respectively formed in the plurality of upper unit molds.

Abstract: A semiconductor device includes a plurality of first signal lines and a plurality of second signal lines which are alternately arranged adjacent to each other, wherein the first signal lines and the second signal lines comprise a plurality of main signal lines and at least one spare signal line, a first signal transmitter suitable for transmitting signals through the main signal lines of the first signal lines, and shifting a signal transmission path to adjacent signal lines among the main signal lines and the spare signal line of the first signal lines, based on repair information, and a second signal transmitter suitable for transmitting signals through the main signal lines of the second signal lines, and shifting a signal transmission path to adjacent signal lines among the main signal lines and the spare signal line of the second signal lines, based on the repair information.

Abstract: A semiconductor device includes a plurality of first signal lines and a plurality of second signal lines which are alternately arranged adjacent to each other, wherein the first signal lines and the second signal lines comprise a plurality of main signal lines and at least one spare signal line, a first signal transmitter suitable for transmitting signals through the main signal lines of the first signal lines, and shifting a signal transmission path to adjacent signal lines among the main signal lines and the spare signal line of the first signal lines, based on repair information, and a second signal transmitter suitable for transmitting signals through the main signal lines of the second signal lines, and shifting a signal transmission path to adjacent signal lines among the main signal lines and the spare signal line of the second signal lines, based on the repair information.

Abstract: Disclosed are a nonspecific immunostimulant composition, a preparation method thereof, and uses thereof. The composition includes 150 to 300 wt. parts of sodium silicate, 2˜8 wt. parts of sodium thiosulfate, 0.5˜2 wt. parts of sodium carbonate, 0.5˜2 wt. parts of potassium chloride, 200˜400 wt. parts of white sugar, and 300˜400 wt. parts of water, based on 100 wt. parts of potassium carbonate. The composition exhibits excellent defense against the mortality caused by AIV H5N1, thus improving the survival of infected animals. As a supplement of a formulated feed mixture for farmed aquatic organisms, the composition provides excellent immunostimulation and disease resistance so as to decrease the mass mortality of aquatic organisms and to increase productivity. Particularly, when raised with a food in mixture with the composition, livestock and farmed aquatic organisms are immunologically improved so that they can endure and are protected against epidemic diseases caused by viruses and bacteria.

Abstract: Disclosed are a nonspecific immunostimulant composition, a preparation method thereof, and uses thereof. The composition includes 150 to 300 wt. parts of sodium silicate, 2˜8 wt. parts of sodium thiosulfate, 0.5˜2 wt. parts of sodium carbonate, 0.5˜2 wt. parts of potassium chloride, 200˜400 wt. parts of white sugar, and 300˜400 wt. parts of water, based on 100 wt. parts of potassium carbonate. The composition exhibits excellent defense against the mortality caused by AIV H5N1, thus improving the survival of infected animals. As a supplement of a formulated feed mixture for farmed aquatic organisms, the composition provides excellent immunostimulation and disease resistance so as to decrease the mass mortality of aquatic organisms and to increase productivity. Particularly, when raised with a food in mixture with the composition, livestock and farmed aquatic organisms are immunologically improved so that they can endure and are protected against epidemic diseases caused by viruses and bacteria.

Abstract: Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor device. The controller generates a power voltage signal. The semiconductor device generates a power-up signal in response to the power voltage signal, generates a first selection pulse, a second selection pulse and an initialization pulse signal, generates a first fuse signal for controlling an internal operation according to a cut state of a first fuse, and generates a second fuse signal for controlling the internal operation according to a cut state of a second fuse.

Abstract: Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor device. The controller generates a power voltage signal. The semiconductor device generates a power-up signal in response to the power voltage signal, generates a first selection pulse, a second selection pulse and an initialization pulse signal, generates a first fuse signal for controlling an internal operation according to a cut state of a first fuse, and generates a second fuse signal for controlling the internal operation according to a cut state of a second fuse.

Abstract: A mobile terminal and an operating method of the mobile terminal are provided. The mobile terminal may be coupled, either wirelessly or by wire, to an external terminal and the mobile terminal may thus receive sync data including information regarding a webpage currently being displayed by the external terminal from the external terminal or a server. The mobile terminal may display the same webpage as is currently being displayed by the external terminal based on the received sync data.

Abstract: A semiconductor memory device includes a latch address generation unit configured to latch row addresses to generate first and second latch addresses when at least one of memory cells coupled to sub word lines is faulty, wherein the first and second latch addresses select different main word lines, and a repair unit configured to perform a repair operation on memory cells coupled to the main word lines selected by the first and second latch addresses.

Abstract: An auto-precharge signal generation circuit comprises a signal generator, a set signal generator, and an auto-precharge signal generator. The signal generator is configured to generating a control signal and a precharge control signal in response to receiving a first column address strobe signal and an auto-precharge flag signal. The set signal generator is configured to generating a set signal in response to receiving the control signal and the precharge control signal. The auto-precharge signal generator is configured to generate an auto-precharge signal in response to receiving the set signal and a period set signal.

Abstract: The present invention provides a primer composition for amplifying a gene region having various variations in a target gene comprising: a first primer group comprising at least one primer specific to at least one template including a genotype-analyzable sequence of a genetically variant base sequence subjected to be analyzed in the target gene; and a second primer group comprising at least one primer designed by selecting one primer having the greatest number of shared bases from the primers of the first primer group and by using the selected primer as a reference, the primer of the second primer group binding specifically to the template or binding complementarily to the template with allowing mismatch of up to three successive bases or 1 to 2 bases in the vicinity of the 3? end of the template.

Abstract: A semiconductor memory device includes a latch address generation unit configured to latch row addresses to generate first and second latch addresses when at least one of memory cells coupled to sub word lines is faulty, wherein the first and second latch addresses select different main word lines, and a repair unit configured to perform a repair operation on memory cells coupled to the main word lines selected by the first and second latch addresses.

Abstract: A semiconductor memory device includes a first sense amplifier which senses data on a first line pair and generates a first output signal; and a test unit which senses the data on a first line pair and transfers a second output signal to a second line in response to a test mode signal.

Abstract: An auto-precharge signal generation circuit comprises a signal generator, a set signal generator, and an auto-precharge signal generator. The signal generator is configured to generating a control signal and a precharge control signal in response to receiving a first column address strobe signal and an auto-precharge flag signal. The set signal generator is configured to generating a set signal in response to receiving the control signal and the precharge control signal. The auto-precharge signal generator is configured to generate an auto-precharge signal in response to receiving the set signal and a period set signal.

Abstract: An auto-precharge signal generation circuit comprises a signal generator, a set signal generator, and an auto-precharge signal generator. The signal generator is configured to generating a control signal and a precharge control signal in response to receiving a first column address strobe signal and an auto-precharge flag signal. The set signal generator is configured to generating a set signal in response to receiving the control signal and the precharge control signal. The auto-precharge signal generator is configured to generate an auto-precharge signal in response to receiving the set signal and a period set signal.

Abstract: A semiconductor memory device includes a first sense amplifier which senses data on a first line pair and generates a first output signal; and a test unit which senses the data on a first line pair and transfers a second output signal to a second line in response to a test mode signal.

Abstract: A semiconductor memory device includes a first sense amplifier which senses data on a first line pair and generates a first output signal; and a test unit which senses the data on a first line pair and transfers a second output signal to a second line in response to a test mode signal.