Abstract: The present technology includes a semiconductor memory device. The semiconductor memory device includes a stack including a conductive pattern and an insulating pattern, a channel structure penetrating the stack, and a memory pattern between the conductive pattern and the channel structure. The memory pattern includes a blocking pattern, a tunnel pattern, a storage pattern, and a ferroelectric pattern.

Abstract: Disclosed is a negative electrode active material which includes: secondary particles having a plurality of primary particles which include a silicon oxide composite including i) Si, ii) a silicon oxide represented by SiOx (0<x?2), and iii) a metal silicate containing Si and M, wherein M is at least one of Li and Mg; and a first carbon coating layer disposed partially or totally on the surfaces of the primary particles to interconnect and fix the primary particles; and a second carbon coating layer disposed on the surfaces of the secondary particles, wherein the second carbon coating layer has higher crystallinity as compared to the first carbon coating layer, and the primary particles have an average particle diameter (D50) of 0.1-3.5 ?m. A negative electrode including the negative electrode active material, and a lithium secondary battery including the negative electrode are also disclosed.

Abstract: A method of testing a radio frequency (RF) integrated circuit includes: forming, performed by the RF integrated circuit, a test loop that passes through a first transceiver circuit, a first front-end circuit, and a second transceiver circuit, based on a test control signal transmitted from a test device; adjusting, performed by the RF integrated circuit, a shift degree of at least one phase shifter in the first front-end circuit, based on the test control circuit; and receiving, performed by the RF integrated circuit, a test input signal via the first transceiver circuit from the test device, and outputting, to the test device, the test input signal that has passed through the test loop, wherein the test input signal is output as a test output signal via the second transceiver circuit.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

Abstract: The present invention relates to efficient signaling of an intra prediction mode for predicting a current block in intra prediction coding. According to an aspect of the present invention, a video encoding apparatus divides dozens of intra modes into groups, selects a group to which an actual intra mode of the current block to be encoded belongs, and signals a value corresponding to the group. The video decoding apparatus acquires information on the group to which the actual intra mode of the current block belongs from a bit-stream and then evaluates intra modes belonging to the group to select a final intra mode.

Abstract: Disclosed herein is a method for adaptive bidirectional optical flow estimation for inter prediction compensation during video encoding. The method aims to reduce complexity and/or cost of bidirectional optical flow (BIO) at a pixel level or a subblock level.

Abstract: The present invention provides a method for preparing a modified and conjugated diene-based polymer, which may prevent processability degradation by restraining the increase of mooney viscosity during post-treatment using steam with high temperature or storage for a long time by stabilizing a modified polymer using a modification stabilizer, and a modified and conjugated diene-based polymer prepared by the preparation method.

Abstract: The present invention relates to an anode active material including natural graphite and mosaic coke-based artificial graphite, and a lithium secondary battery including the same. According to an embodiment of the present invention, an anode active material including natural graphite and mosaic coke-based artificial graphite is used, when applied to a lithium secondary battery, intercalation and deintercalation of lithium ions is more facilitated and conductivity of an electrode is improved even if no or little conductive material is used. Furthermore, the increase in conductivity can lead to not only a further improvement in rate performance of a lithium secondary battery but also a reduction in interfacial resistance.

Abstract: Disclosed herein is a method of encoding prediction information about a current block located in a first face to be encoded in encoding each face of a 2D image onto which 360 video is projected. The method includes generating prediction information candidates using neighboring blocks around the current block; and encoding a syntax element for the prediction information about the current block using the prediction information candidates. When a border of the current block coincides with a border of the first face, a block adjoining the current block based on the 360 video rather than the 2D image is set as at least a part of the neighboring blocks.

Abstract: A method of manufacturing a semiconductor device includes forming a first sacrificial layer including a nitride over a first source layer, forming a second sacrificial layer including aluminum oxide over the first sacrificial layer, forming a second source layer over the second sacrificial layer, forming a stacked structure over the second source layer, forming a channel layer that passes through the stacked structure, the second source layer, the second sacrificial layer, and the first sacrificial layer, the channel layer being enclosed by a memory layer, forming a slit that passes through the stacked structure and the second source layer, forming a polysilicon spacer in the slit, forming an opening by removing the first sacrificial layer and the second sacrificial layer, exposing the channel layer by etching the memory layer, and forming a third source layer in the opening.

Abstract: A display device comprising: a substrate; a plurality of display elements disposed on the substrate; and a diffraction pattern layer disposed on a path of light emitted from the plurality of display elements. The diffraction pattern layer comprises a plurality of diffraction patterns which is disposed with a predetermined pitch, and the plurality of diffraction patterns do not overlap the plurality of display elements; and when a width of a cross section of each of the plurality of diffraction patterns is defined as a length of each diffraction pattern, the predetermined pitch and the length of each diffraction pattern satisfy the following inequation: 0.4?d1/DP1<1, where DP1 denotes the predetermined pitch, and d1 denotes the length of each diffraction pattern.

Abstract: Disclosed herein is a method for adaptive bidirectional optical flow estimation for inter-screen prediction compensation during video encoding. The method aims to reduce complexity and/or cost of bidirectional optical flow (BIO) at a pixel level or a subblock level.

Abstract: The present invention relates to a 5th-generation (5G) or pre-5G communication system to be provided in order to support a higher data transmission rate than a beyond 4th-generation (4G) communication system such as long term evolution (LTE). The present invention relates to a signal transmission method of a radio frequency (RF) processing device, the method comprising the steps of: generating a pulse signal including a control signal and a clock signal for obtaining synchronization with another RF processing device, which is connected through an interface; and transmitting, to the another RF processing device, at least one from among the pulse signal, a RF signal for communication with a base station, and a power signal for supplying power to the another RF processing device, wherein the clock signal and the control signal are assigned to different time units, and the pulse signal, the RF signal and the power signal are signals of different frequency bands.

Abstract: The present disclosure relates to video encoding or decoding for splitting a picture into a plurality of tiles in order to encode video efficiently. In one aspect of the present disclosure, a video encoding method for encoding a picture split into a plurality of tiles includes encoding first information indicating whether to merge some of the plurality of tiles; when the first information is encoded to indicate tile merging, generating one or more merge tiles by merging some of the plurality of tiles, each of the merge tiles being defined as one tile; encoding second information indicating tiles merged into each of the merge tiles among the plurality of tiles; and encoding each of the merge tiles as one tile without restriction on encoding dependencies between the tiles merged into each of the merge tiles.

Abstract: Disclosed is a negative electrode active material which includes: a silicon oxide composite including i) Si, ii) a silicon oxide represented by SiOx (0<x?2), and iii) magnesium silicate containing Si and Mg; and a carbon coating layer positioned on the surface of the silicon oxide composite and including a carbonaceous material, wherein X-ray diffractometry of the negative electrode active material shows peaks of Mg2SiO4 and MgSiO3 at the same time and shows no peak of MgO; and the ratio of peak intensity, I (Mg2SiO4)/I (MgSiO3), which is intensity I (Mg2SiO4) of peaks that belong to Mg2SiO4 to intensity I (MgSiO3) of peaks that belong to MgSiO3 is smaller than 1, the peaks that belong to Mg2SiO4 are observed at 2?=32.2±0.2°, and the peaks that belong to MgSiO3 are observed at 2?=30.9±0.2°.

Abstract: The present invention provides a compound that can increase the light-emitting efficiency, reduce the driving voltage, and improve the durability of an element, an organic electronic element using the same, and an electronic device thereof.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

Abstract: The present application relates to an optical filter and an organic light-emitting display device. The optical filter of the present application has excellent omnidirectional antireflection performance on the side as well as the front. The optical filter can be applied to an organic light-emitting device to improve visibility.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.