Patents by Inventor Sunanda Manjunath

Sunanda Manjunath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11881861
    Abstract: Some examples relate to a system including a pulse modulation (PM) circuit having a PM input and a PM output. The system also includes a load circuit having a load circuit input, and an I/O pad coupling the PM output to the load circuit input. An asymmetry detection circuit has a first asymmetry detection (AD) input coupled to the PM output via a first feedback path, a second AD input coupled to an output node of the I/O pad via a second feedback path, and an AD output coupled to the PM input of the pulse modulation circuit via a control path.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: January 23, 2024
    Assignee: Infineon Technologies AG
    Inventors: Sunanda Manjunath, Ketan Dewan, Juergen Schaefer
  • Publication number: 20230238949
    Abstract: Some examples relate to a system including a pulse modulation (PM) circuit having a PM input and a PM output. The system also includes a load circuit having a load circuit input, and an I/O pad coupling the PM output to the load circuit input. An asymmetry detection circuit has a first asymmetry detection (AD) input coupled to the PM output via a first feedback path, a second AD input coupled to an output node of the I/O pad via a second feedback path, and an AD output coupled to the PM input of the pulse modulation circuit via a control path.
    Type: Application
    Filed: January 26, 2022
    Publication date: July 27, 2023
    Inventors: Sunanda Manjunath, Ketan Dewan, Juergen Schaefer
  • Patent number: 11640332
    Abstract: Systems, methods, and circuitries are provided for checking integrity of code received from an external memory. In one example, a system includes a non-volatile memory and a controller. The non-volatile memory includes a first partition configured to store first data corresponding to program code and a second partition configured to store second data corresponding to a copy of the first data. The controller that includes a processor and comparator circuitry. The comparator circuitry is configured to receive a portion of the first data and a corresponding portion of the second data, compare the portion of the first data to the portion of the second data, when the portion of the first data matches the portion of the second data, provide the portion of the first data to the processor, and when the portion of the first data does not match the portion of the second data, generate an alarm signal.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: May 2, 2023
    Assignee: Infineon Technologies AG
    Inventors: Sunanda Manjunath, Jens Rosenbusch
  • Publication number: 20230123080
    Abstract: Systems, methods, and circuitries are provided for checking integrity of code received from an external memory. In one example, a system includes a non-volatile memory and a controller. The non-volatile memory includes a first partition configured to store first data corresponding to program code and a second partition configured to store second data corresponding to a copy of the first data. The controller that includes a processor and comparator circuitry. The comparator circuitry is configured to receive a portion of the first data and a corresponding portion of the second data, compare the portion of the first data to the portion of the second data, when the portion of the first data matches the portion of the second data, provide the portion of the first data to the processor, and when the portion of the first data does not match the portion of the second data, generate an alarm signal.
    Type: Application
    Filed: October 15, 2021
    Publication date: April 20, 2023
    Inventors: Sunanda Manjunath, Jens Rosenbusch