Patents by Inventor Sunao Aya

Sunao Aya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10043635
    Abstract: A vacuum is maintained inside a vacuum partition (1). The whole of the solid packed container (3) is disposed inside the vacuum partition (1). A heater (7) sublimates the aluminum chloride (8) packed in the solid packed container (3) to generate an aluminum chloride gas (9). An arc chamber (6) ionizes the aluminum chloride gas (9) and emits an ion beam (11) of the ionized aluminum chloride gas (9). A gas supply nozzle (10) leads the aluminum chloride gas (9) from the solid packed container (3) into the arc chamber (6). A supporting part (4) supports and fixes the solid packed container (3) on the vacuum partition (1). A thermal conductivity of the supporting part (4) is lower than thermal conductivities of the vacuum partition (1) and the solid packed container (3).
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: August 7, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Sunao Aya
  • Publication number: 20170133201
    Abstract: A vacuum is maintained inside a vacuum partition (1). The whole of the solid packed container (3) is disposed inside the vacuum partition (1). A heater (7) sublimates the aluminum chloride (8) packed in lid packed container (3) to generate an aluminum chloride gas (9). An arc chamber (6) ionizes the aluminum chloride gas (9) and emits an ion beam (11) of the ionized aluminum chloride gas (9). A gas supply nozzle (10) leads the aluminum oride gas (9) from the solid packed container (3) into the arc chamber (6). A supporting part (4) supports and fixes the solid packed container (3) on the vacuum partition (1). A thermal conductivity of the supporting part (4) is lower than thermal conductivities of the vacuum partition (1) and the solid packed container (3).
    Type: Application
    Filed: September 25, 2014
    Publication date: May 11, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventor: Sunao AYA
  • Patent number: 9188872
    Abstract: A method for manufacturing a semiconductor device includes a photolithography process having steps of a developing solution immersing process. The steps of the developing solution immersing process includes step (a) of dropping a developing solution on a silicon carbide semiconductor substrate and forming a developing solution film so as to have a film thickness of more than 6 ?m and step (b) of reducing the film thickness of the developing solution film to 6 ?m or less.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: November 17, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Sunao Aya, Shozo Shikama, Hideaki Yuki
  • Patent number: 9093361
    Abstract: A semiconductor device capable of suppressing time variation of a threshold voltage and a method of manufacturing the same. A semiconductor device according to the present invention comprises a drift layer formed on a semiconductor substrate, first well regions formed in a surface layer of the drift layer, being apart from one another, a gate insulating film formed, extending on the drift layer and each of the first well regions, a gate electrode selectively formed on the gate insulating film, a source contact hole penetrating through the gate insulating film and reaching the inside of each of the first well regions, and a residual compressive stress layer formed on at least a side surface of the source contact hole, in which a compressive stress remains.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: July 28, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shiro Hino, Naruhisa Miura, Akihiko Furukawa, Yukiyasu Nakao, Tomokatsu Watanabe, Masayoshi Tarutani, Yuji Ebiike, Masayuki Imaizumi, Sunao Aya
  • Patent number: 9063428
    Abstract: A method for manufacturing a semiconductor device of the present invention includes steps of (a) preparing a silicon carbide substrate including a photoresist film formed on a principal surface, (b) dropping a first developing solution onto the photoresist film, (c) rotating the silicon carbide substrate to drain the first developing solution dropped onto the photoresist film after a lapse of a first development time since the end of the step (b), (d) dropping a second developing solution onto the photoresist film after the step (c), and (e) rotating the silicon carbide substrate to drain the second developing solution dropped onto the photoresist film after a lapse of a second development time since the end of the step (d).
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: June 23, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hideaki Yuki, Sunao Aya, Shozo Shikama
  • Patent number: 9059086
    Abstract: A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (d) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: June 16, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuji Ebiike, Takahiro Nakatani, Hiroshi Watanabe, Yoshio Fujii, Sunao Aya, Yoshiyuki Nakaki, Tsuyoshi Kawakami, Shuhei Nakata
  • Publication number: 20140377709
    Abstract: A method for manufacturing a semiconductor device of the present invention includes steps of (a) preparing a silicon carbide substrate including a photoresist film formed on a principal surface, (b) dropping a first developing solution onto the photoresist film, (c) rotating the silicon carbide substrate to drain the first developing solution dropped onto the photoresist film after a lapse of a first development time since the end of the step (b), (d) dropping a second developing solution onto the photoresist film after the step (c), and (e) rotating the silicon carbide substrate to drain the second developing solution dropped onto the photoresist film after a lapse of a second development time since the end of the step (d).
    Type: Application
    Filed: April 2, 2014
    Publication date: December 25, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hideaki YUKI, Sunao AYA, Shozo SHIKAMA
  • Publication number: 20140370445
    Abstract: A method for manufacturing a semiconductor device includes a photolithography process having steps of a developing solution immersing process. The steps of the developing solution immersing process includes step (a) of dropping a developing solution on a silicon carbide semiconductor substrate and forming a developing solution film so as to have a film thickness of more than 6 ?m and step (b) of reducing the film thickness of the developing solution film to 6 ?m or less.
    Type: Application
    Filed: April 1, 2014
    Publication date: December 18, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Sunao AYA, Shozo SHIKAMA, Hideaki YUKI
  • Publication number: 20140077232
    Abstract: A semiconductor device capable of suppressing time variation of a threshold voltage and a method of manufacturing the same. A semiconductor device according to the present invention comprises a drift layer formed on a semiconductor substrate, first well regions formed in a surface layer of the drift layer, being apart from one another, a gate insulating film formed, extending on the drift layer and each of the first well regions, a gate electrode selectively formed on the gate insulating film, a source contact hole penetrating through the gate insulating film and reaching the inside of each of the first well regions, and a residual compressive stress layer formed on at least a side surface of the source contact hole, in which a compressive stress remains.
    Type: Application
    Filed: March 7, 2012
    Publication date: March 20, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Shiro Hino, Naruhisa Miura, Akihiko Furukawa, Yukiyasu Nakao, Tomokatsu Watanabe, Masayoshi Tarutani, Yuji Ebiike, Masayuki Imaizumi, Sunao Aya
  • Publication number: 20130288467
    Abstract: A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (c) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer.
    Type: Application
    Filed: June 9, 2011
    Publication date: October 31, 2013
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuji Ebiike, Takahiro Nakatani, Hiroshi Watanabe, Yoshio Fujii, Sunao Aya, Yoshiyuki Nakaki, Tsuyoshi Kawakami, Shuhei Nakata
  • Patent number: 8252672
    Abstract: A method of manufacturing a silicon carbide semiconductor device having a silicon carbide layer, the method including a step of implanting at least one of Al ions, B ions and Ga ions having an implantation concentration in a range not lower than 1E19 cm?3 and not higher than 1E21 cm?3 from a main surface of the silicon carbide layer toward the inside of the silicon carbide layer while maintaining the temperature of the silicon carbide layer at 175° C. or higher, to form a p-type impurity layer; and forming a contact electrode whose back surface establishes ohmic contact with a front surface of the p-type impurity layer on the front surface of the p-type impurity layer.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: August 28, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tomokatsu Watanabe, Sunao Aya, Naruhisa Miura, Keiko Sakai, Shohei Yoshida, Toshikazu Tanioka, Yukiyasu Nakao, Yoichiro Tarui, Masayuki Imaizumi
  • Publication number: 20090250705
    Abstract: A p base ohmic contact of a silicon carbide semiconductor device consists of a p++ layer formed by high-concentration ion implantation and a metal electrode. Since the high-concentration ion implantation performed at the room temperature significantly degrades the crystal of the p++ layer to cause a process failure, a method for implantation at high temperatures is used. In terms of switching loss and the like of devices, it is desirable that the resistivity of the p base ohmic contact should be lower. In well-known techniques, nothing is mentioned on a detailed relation among the ion implantation temperature, the ohmic contact resistivity and the process failure. Then, in the ion implantation step, the temperature of a silicon carbide wafer is maintained in a range from 175° C. to 300° C., more preferably in a range from 175° C. to 200° C. The resistivity of the p base ohmic contact using a p++ region formed by ion implantation at a temperature in a range from 175° C. to 300° C.
    Type: Application
    Filed: November 7, 2008
    Publication date: October 8, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tomokatsu WATANABE, Sunao Aya, Naruhisa Miura, Keiko Sakai, Shohei Yoshida, Toshikazu Tanioka, Yukiyasu Nakao, Yoichiro Tarui, Masayuki Imaizumi
  • Patent number: 6265113
    Abstract: An X-ray absorber is deposited on a membrane. A stress adjust step is applied so that the average film stress of the X-ray absorber is 0. After patterning the X-ray absorber, the position accuracy of the pattern is measured. Then, a stress adjust process is applied to the patterned X-ray mask. Accordingly, a stress adjustment method is used to acquire an X-ray mask that has no pattern position offset of the X-ray absorber.
    Type: Grant
    Filed: July 16, 1998
    Date of Patent: July 24, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideki Yabe, Kaeko Kitamura, Kenji Marumoto, Sunao Aya, Koji Kise
  • Patent number: 6212252
    Abstract: An X-ray mask which is provided with an alignment mark and a transfer circuit pattern having a high position accuracy can be manufactured through a simplified manufacturing process. A membrane allowing passage of X-rays is formed on a substrate. A X-ray absorber intercepting transmission of X-rays is formed on the membrane. The substrate includes a window exposing the membrane. The X-ray absorber includes a transfer circuit pattern and an alignment mark formed in a region not overlapping with the window in a plan view.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: April 3, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Koji Kise, Hideki Yabe, Sunao Aya, Kaeko Kitamura, Kenji Marumoto, Shigeto Ami
  • Patent number: 6190808
    Abstract: An X-ray mask including a transfer pattern having high accuracy is obtained. In a method of manufacturing the X-ray mask, an X-ray absorber film preventing transmission of an X-ray is formed on a substrate. A resist film is formed on the X-ray absorber film. The substrate is placed on a movable member. Steps of moving the movable member and irradiating the resist film with an energy beam are repeated for carrying out a drawing step of drawing a pattern on the resist film. Between the step of placing the substrate on the movable member and the drawing step, a step of holding a mask member including the resist film, the X-ray absorber film and the substrate to be in a state substantially identical to thermal equilibrium in the drawing step is carried out.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: February 20, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Koji Kise, Sunao Aya, Takaaki Murakami
  • Patent number: 5953492
    Abstract: The X-ray mask manufactured according to the present invention can solve a problem that the thin film stress of the X-ray absorber cannot be made to be zero although the mean thin film stress throughout the X-ray absorber can be made to be zero. The thin film stress distribution over the X-ray absorber 4 after the X-ray absorber 4 has been formed on a silicon substrate 1 is measured, and then inputs of electric power to heaters 9a, 9b and 9c of a hot plate 8 are changed so as to heat the X-ray absorber 4 to temperatures according to a specified temperature distribution with which the thin film stress throughout the X-ray absorber can be made to be zero.
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: September 14, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideki Yabe, Kenji Marumoto, Sunao Aya, Koji Kise, Hiroaki Sumitani, Takashi Hifumi, Hiroshi Watanabe
  • Patent number: 5834142
    Abstract: The X-ray mask manufactured according to the present invention can solve a problem that the thin film stress of the X-ray absorber cannot be made to be zero although the mean thin film stress throughout the X-ray absorber can be made to be zero. The thin film stress distribution over the X-ray absorber 4 after the X-ray absorber 4 has been formed on a silicon substrate 1 is measured, and then inputs of electric power to heaters 9a, 9b and 9c of a hot plate 8 are changed so as to heat the X-ray absorber 4 to temperatures according to a specified temperature distribution with which the thin film stress throughout the X-ray absorber can be made to be zero.
    Type: Grant
    Filed: October 25, 1996
    Date of Patent: November 10, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideki Yabe, Kenji Marumoto, Sunao Aya, Koji Kise, Hiroaki Sumitani, Takashi Hifumi, Hiroshi Watanabe
  • Patent number: 5677090
    Abstract: A method of making a X-ray mask including: a step of forming a X-ray absorber above a substrate; a step of controlling a stress of the X-ray absorber by a predetermined condition; and wherein the predetermined condition for controlling the stress of the X-ray absorber formed above the substrate is determined by a measured value of a stress of a X-ray absorber formed on a monitor substrate.
    Type: Grant
    Filed: February 21, 1996
    Date of Patent: October 14, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kenji Marumoto, Hideki Yabe, Sunao Aya, Koji Kise, Kei Sasaki