Abstract: Disclosed herein is a hysteresis comparator for performing a binarization determination with respect to an input signal having a consecutively varying voltage level based on two threshold voltages having different voltage levels and generating an output signal based on a result of the determination.

Abstract: A delayed peak detector detects a peak level of an input signal IN at timing lagged behind a peak detector, and a peak difference detector detects a peak difference PLD between a delayed peak level DPL and a peak level PL. A reset portion outputs a reset signal BRS for a bottom detector when a level difference between the peak level PL and a bottom level BL exceeds a predetermined value comparable with the amplitude of the input signal IN and the peak difference PLD exceeds an allowable peak difference PLM. It is thus possible to replace the bottom level BL outputted from the bottom detector with a bottom level based on a latest input signal IN.

Abstract: A delayed peak detector detects a peak level of an input signal IN at timing lagged behind a peak detector, and a peak difference detector detects a peak difference PLD between a delayed peak level DPL and a peak level PL. A reset portion outputs a reset signal BRS for a bottom detector when a level difference between the peak level PL and a bottom level BL exceeds a predetermined value comparable with the amplitude of the input signal IN and the peak difference PLD exceeds an allowable peak difference PLM. It is thus possible to replace the bottom level BL outputted from the bottom detector with a bottom level based on a latest input signal IN.

Abstract: A demodulating circuit includes a differentiating circuit that outputs a differentiated signal indicating voltage changes at rising and falling edges of a received pulse signal, and a hysteresis comparator that compares the differentiated signal with upper and lower threshold voltages, thereby generating a demodulated logic-level signal. The differentiating circuit can rapidly track variations in the direct-current offset of the received pulse signal. Positive feedback can enable the hysteresis comparator to maintain the correct output logic level during runs of 0's or 1's of arbitrary length in the received pulse signal. The demodulating circuit consumes comparatively little power, and is particularly useful for receiving signals transmitted in bursts.

Abstract: A demodulating circuit includes a differentiating circuit that outputs a differentiated signal indicating voltage changes at rising and falling edges of a received pulse signal, and a hysteresis comparator that compares the differentiated signal with upper and lower threshold voltages, thereby generating a demodulated logic-level signal. The differentiating circuit can rapidly track variations in the direct-current offset of the received pulse signal. Positive feedback can enable the hysteresis comparator to maintain the correct output logic level during runs of 0's or 1's of arbitrary length in the received pulse signal. The demodulating circuit consumes comparatively little power, and is particularly useful for receiving signals transmitted in bursts.

Abstract: Disclosed is an offset voltage cancellation circuit that can quickly cope with a change in the state and can cancel an offset voltage for differential signals. Peak voltages VP1 and VP2 of differential input signals VA1 and VA2 are retained in capacitors 12 of peak detectors 101 and 102. An adder 201 adds the differential input signal VA1 to the peak voltage VP2 to obtain a differential output signal VC1, while an adder 202 adds the differential input signal VA2 to the peak voltage VP1 to obtain a differential output signal VC2. The differential output voltages VC1 and VC2 are transmitted to a peak level reset unit 30 to generate a reset signal RST that is consonant with the potential difference, and the reset signal RST is transmitted to the gates of NMOSes 14 of the peak detectors 101 and 102. When an offset occurs between the differential output signals VC1 and VC2, the level of the reset signal RST is increased, and the NMOSes 14 are rendered conducive.

Abstract: Disclosed is an offset voltage cancellation circuit that can quickly cope with a change in the state and can cancel an offset voltage for differential signals. Peak voltages VP1 and VP2 of differential input signals VA1 and VA2 are retained in capacitors 12 of peak detectors 101 and 102. An adder 201 adds the differential input signal VA1 to the peak voltage VP2 to obtain a differential output signal VC1, while an adder 202 adds the differential input signal VA2 to the peak voltage VP1 to obtain a differential output signal VC2. The differential output voltages VC1 and VC2 are transmitted to a peak level reset unit 30 to generate a reset signal RST that is consonant with the potential difference, and the reset signal RST is transmitted to the gates of NMOSes 14 of the peak detectors 101 and 102. When an offset occurs between the differential output signals VC1 and VC2, the level of the reset signal RST is increased, and the NMOSes 14 are rendered conducive.

Abstract: An input terminal of an amplifier circuit is connected to a base terminal of an amplifying transistor, and is also connected to one of the terminals of capacitor via a first wiring. An output terminal of the amplifier circuit is connected to a collector terminal of the amplifying transistor, to the other terminal of the capacitor via a second wiring and also to a source voltage via a load resistor. An emitter terminal of the amplifying transistor is connected to ground via a feedback resistor. The second wiring connecting the other terminal of the capacitor and the collector terminal of the amplifying transistor is formed to intersect a cutting line, or a so-called grid line, of the wafer which is used as reference for dicing the wafer into chips.

Abstract: A coupling capacitor 21 is connected in parallel to a diode 23 between an output nord N1 of a differential amplifier circuit 10 and an input nord N3 of another differential amplifier circuit 50. In a test mode, when a test signal TC is applied to a test pad 43, a switch circuit 40 is turned on to shortcircuit a bias resistor 35 thus decreasing a bias potential at the input nord N3. This causes the diode 23 to switch on for amplifying a test low-frequency input signal IN with the differential amplifier circuit 10. By the action of the diode 23, an output of the differential amplifier circuit 10 is bypassed to the differential amplifier circuit 50. The two differential amplifier circuits 10 and 50 can thus be inspected substantially by examining an output signal OUT obtained through an output pad 56 of the differential amplifier circuit 50.