Abstract: A multi connector device comprising a plurality of connector pairs of first connectors and second connectors mating therewith, and a multi-connector support housing for accommodating the connector pairs. The multi-connector support housing comprises a support housing defining a plurality of connector accommodating chambers therein which are arranged in order and accommodate the connector pairs therein, respectively. A plurality of pairs of guide engaging portions are formed on the support housing at the connector accommodating chambers and engaging the connector pairs accommodated in the chambers and guiding the connector pairs to move in connecting and disconnecting directions in the chambers, respectively. A slider as a connector driving member is removably assembled onto the support housing to drive the connector pairs in a selected one of the connecting and disconnecting directions.

Abstract: A microprogram controller in a data processing apparatus includes a control storage device which has ECC bits and tri-state input/output pins, a first register for holding microprogram data read out from the control storage device and all the bits of the ECC data, an error detection/correction circuit for performing an ECC check operation on the basis of an output value of the first register and correcting a correctable error, second to Nth registers for holding only some bits of the microprogram data read out from the control storage device, and a data bus for connecting the control storage device, an input and an output of the first register, and inputs of the second to Nth registers. When a correctable error is detected on the basis of the output value of the first register, data corrected by the error detection/correction circuit is sent onto the data bus, and the second to Nth registers fetch the corrected data from the data bus.

Abstract: A vector processor which maintains synchronization with an associated CPU by limiting the operational instruction proceedings. The vector processor utilizes an instruction register to store instructions from the CPU logical operations circuitry word processing in parallel with the CPU in accordance with instructions from the instruction register and a counter which increases in response to a start instruction from the CPU and decreases in response to the completion of an operation by the logical operation circuitry. A restraining signal is generated in response to a prescribed count of the counter, which delays the execution of the microprogram by the CPU. An indicator device is used for indicating storage of an instruction in the instruction register and a flag device is set in response to a start instruction from the CPU which actuates the indicator means even if no instruction is stored in the instruction register.

Abstract: A vector arithmetic processor includes a register file for storing an operand of an instruction supplied from a CPU, at least one pointer register for storing address data for the register file, and a scalar control register for storing a signal representing whether an operand is a vector or scalar operand. This at least one pointer register is arranged such that the current value is retained and fed back and the fed back value is used in the second and subsequent cycles when the value of the scalar control register represents a scalar value.

Abstract: A system for controlling polynomial arithmetic operations of a vector arithmetic processor capable of executing the arithmetic operations independently of a central processing unit (CPU), includes, in the vector arithmetic processor, a circuit for modifying an instruction code supplied from the CPU on the basis of a signal representing that the instruction supplied from the CPU is a vector arithmetic instruction and a signal for commanding switching of the instruction code from the CPU, and an instruction decoder addressed in response to an output from the modification circuit to output an instruction word to an arithmetic unit.