Patents by Inventor Sundar Kumar Iyer
Sundar Kumar Iyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6998865Abstract: A test arrangement includes a semiconductor device, a first conductive pad electrically connected to the semiconductor device, a second conductive pad, and a programmable fuse. The second conductive pad is electrically connected to the semiconductor device through the programmable fuse.Type: GrantFiled: December 10, 2001Date of Patent: February 14, 2006Assignee: International Business Machines CorporationInventors: Karen A. Bard, S. Sundar Kumar Iyer
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Patent number: 6781436Abstract: A transistor (such as a MOSFET) is operated in its breakdown region, as opposed to its saturation region, to program an electric fuse. With the programming transistor operated in the breakdown region, a much higher current is enabled than the associated saturation current for the same size transistor. Thus, a smaller transistor can be used for programming the fuse. Cooperative with transistor operation in the breakdown region, a dynamic current compliance device is used to limit the peak current to prevent damage than can result from excessive current flowing through the transistor. The current compliance device can be external to the integrated fuse and programming transistor circuit.Type: GrantFiled: July 25, 2002Date of Patent: August 24, 2004Assignee: Infineon Technologies AGInventors: Chandrasekharan Kothandaraman, S. Sundar Kumar Iyer
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Publication number: 20040056703Abstract: A transistor (such as a MOSFET) is operated with the well biased, as opposed to being grounded, to program an electric fuse. With the programming transistor operated with an active well bias, more energy is enabled for programming the fuse than is available with a grounded well for the same size transistor. Thus, a smaller transistor can be used of programming the fuse. In a multiple fuse embodiment, the programming transistors can be arranged in the same “well” with a common independent Vbias applied, via a body control circuit, to the entire well during programming of a select fuse.Type: ApplicationFiled: September 19, 2002Publication date: March 25, 2004Inventors: Chandrasekharan Kothandaraman, S. Sundar Kumar Iyer
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Patent number: 6710640Abstract: A transistor (such as a MOSFET) is operated with the well biased, as opposed to being grounded, to program an electric fuse. With the programming transistor operated with an active well bias, more energy is enabled for programming the fuse than is available with a grounded well for the same size transistor. Thus, a smaller transistor can be used of programming the fuse. In a multiple fuse embodiment, the programming transistors can be arranged in the same “well” with a common independent Vbias applied, via a body control circuit, to the entire well during programming of a select fuse.Type: GrantFiled: September 19, 2002Date of Patent: March 23, 2004Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Chandrasekharan Kothandaraman, S. Sundar Kumar Iyer
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Publication number: 20040017246Abstract: A transistor (such as a MOSFET) is operated in its breakdown region, as opposed to its saturation region, to program an electric fuse. With the programming transistor operated in the breakdown region, a much higher current is enabled than the associated saturation current for the same size transistor. Thus, a smaller transistor can be used for programming the fuse. Cooperative with transistor operation in the breakdown region, a dynamic current compliance device is used to limit the peak current to prevent damage than can result from excessive current flowing through the transistor. The current compliance device can be external to the integrated fuse and programming transistor circuit.Type: ApplicationFiled: July 25, 2002Publication date: January 29, 2004Inventors: Chandrasekharan Kothandaraman, S. Sundar Kumar Iyer
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Patent number: 6624499Abstract: The present invention provides a system, apparatus and method of programming via electromigration. A semiconductor fuse which includes a cathode and an anode coupled by a fuse link having an electrically conductive component, such as silicide, is coupled to a power supply. A potential is applied across the conductive fuse link via the cathode and anode in which the potential is of a magnitude to initiate electromigration of silicide from a region of the semiconductor fuse reducing the conductivity of the fuse link. The electromigration is enhanced by effectuating a temperature gradient between the fuse link and one of the cathode and anode responsive to the applied potential. Portions of the semiconductor fuse are selectively cooled in a heat transfer relationship to increase the temperature gradient. In one embodiment, a heat sink is applied to the cathode. The heat sink can be a layer of metal coupled in close proximity to the cathode while insulated from the fuse link.Type: GrantFiled: September 19, 2002Date of Patent: September 23, 2003Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Chandrasekharan Kothandaraman, S. Sundar Kumar Iyer, Subramanian Iyer, Chandrasekhar Narayan
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Publication number: 20030160297Abstract: The present invention provides a system, apparatus and method of programming via electromigration. A semiconductor fuse which includes a cathode and an anode coupled by a fuse link having an electrically conductive component, such as silicide, is coupled to a power supply. A potential is applied across the conductive fuse link via the cathode and anode in which the potential is of a magnitude to initiate electromigration of silicide from a region of the semiconductor fuse reducing the conductivity of the fuse link. The electromigration is enhanced by effectuating a temperature gradient between the fuse link and one of the cathode and anode responsive to the applied potential. Portions of the semiconductor fuse are selectively cooled in a heat transfer relationship to increase the temperature gradient. In one embodiment, a heat sink is applied to the cathode. The heat sink can be a layer of metal coupled in close proximity to the cathode while insulated from the fuse link.Type: ApplicationFiled: September 19, 2002Publication date: August 28, 2003Inventors: Chandrasekharan Kothandaraman, S. Sundar Kumar Iyer, Subramanian Iyer, Chandrasekhar Narayan
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Publication number: 20030107391Abstract: A test arrangement includes a semiconductor device, a first conductive pad electrically connected to the semiconductor device, a second conductive pad, and a programmable fuse. The second conductive pad is electrically connected to the semiconductor device through the programmable fuse.Type: ApplicationFiled: December 10, 2001Publication date: June 12, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karen A. Bard, S. Sundar Kumar Iyer
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Publication number: 20020197836Abstract: A method for forming variable oxide thicknesses across semiconductor chips comprises providing a silicon semiconductor substrate having pre-selected areas open to silicon surface using a photoresist layer; immersing the silicon semiconductor substrate in an HF type electrolytic bath to produce a porous silicon area; and removing the photoresist layer and oxidizing the silicon semiconductor substrate to produce a plurality of thicknesses of gate oxide on the silicon semiconductor substrate.Type: ApplicationFiled: June 11, 2001Publication date: December 26, 2002Applicant: International Business Machines CorporationInventors: S. Sundar Kumar Iyer, Suryanarayan G. Hegde, Erin Catherine Jones, Harald F. Okorn-Schmidt
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Patent number: 6486043Abstract: A method for forming a semiconductor devices structure includes providing a semiconductor substrate, forming a deep trench continuously in the substrate to separate a first region from a second region, and then forming a silicon-on-insulator region in the first region while maintaining a non-silicon-on-insulator region in the second region. The deep trench has a depth which is at least as deep as the depth of the buried oxide in the substrate. The invention also includes a device structure resulting from the method.Type: GrantFiled: August 31, 2000Date of Patent: November 26, 2002Assignee: International Business Machines CorporationInventors: Robert Hannon, Herbert L. Ho, Subramanian Iyer, S. Sundar Kumar Iyer
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Patent number: 6368902Abstract: Described herein is a fuse incorporating a covering layer disposed on a conductive layer, which is disposed on a polysilicon layer. The covering layer preferably comprises a relatively inert material, such as a nitride etchant barrier. The covering layer preferably has a region of relatively less-inert filler material. Upon programming of the fuse, the conductive layer, which can be a silicide, preferentially degrades in the region underlying the filler material of the covering layer. This preferential degradation results in a predictable “blowing” of the fuse in the fuse region underlying the filler material. Since the “blow” area is predictable, damage to adjacent structures can be minimized or eliminated.Type: GrantFiled: May 30, 2000Date of Patent: April 9, 2002Assignee: International Business Machines CorporationInventors: Chandrasekharan Kothandaraman, Frank Grellner, Sundar Kumar Iyer
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Patent number: 6096580Abstract: A low programming voltage anti-fuse formed by a MOSFET (or MOS) or by a deep trench (DT) capacitor structure is described. Lowering the programming voltage is achieved by implanting a dose of heavy ions, such as indium, into the dielectric directly on the substrate or indirectly through a layer of polysilicon. The programming voltage can also be lowered on the MOSFET/MOS capacitor anti-fuse by accentuating the corners of active areas and gate areas of the device with suitable layout masks during processing. Silicon active area corner rounding steps should also be avoided in the fabrication of the anti-fuse to reduce the programming voltage. In the DT capacitor, lowering the programming voltage may be achieved by implanting the node dielectric of the DT anti-fuse with heavy ions either directly or through a conformal layer of polysilicon deposited on it or after the first amorphous silicon recess step during the fabrication of the DT capacitor.Type: GrantFiled: September 24, 1999Date of Patent: August 1, 2000Assignee: International Business Machines CorporationInventors: S. Sundar Kumar Iyer, Liang-Kai Han, Robert Hannon, Subramanian S. Iyer, Mukesh V. Khare