Patents by Inventor Sundar V. PATHY

Sundar V. PATHY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Compressed test patterns for a field programmable gate array
    Patent number: 11193975
    Abstract: Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 7, 2021
    Assignee: Intel Corportion
    Inventors: Christopher J. Nelson, Shelby G. Rollins, Hiren V. Tilala, Matthew Hendricks, Sundar V. Pathy, Timothy J. Callahan, Jared Pager, James Neeb, Bradly Inman, Stephen Sturges
  • COMPRESSED TEST PATTERNS FOR A FIELD PROGRAMMABLE GATE ARRAY
    Publication number: 20200003836
    Abstract: Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Christopher J. NELSON, Shelby G. ROLLINS, Hiren V. TILALA, Matthew HENDRICKS, Sundar V. PATHY, Timothy J. CALLAHAN, Jared PAGER, James NEEB, Bradly INMAN, Stephen STURGES