Patents by Inventor SUNDARA RAGHAVAN SANKARAN

SUNDARA RAGHAVAN SANKARAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9767231
    Abstract: Methods and systems for measuring relatedness, known as net affinity, between any two arbitrary nodes, known as entities, in a graph is provided. According to one embodiment, unprocessed data about entities is collected from various data sources. The unprocessed data is transformed to a graph with entities as nodes and corresponding direct affinities between them as edges. Depending on relationship between corresponding nodes, the corresponding edges are at least one of non-directed, directed and temporal. The graph is simulated as an electrical circuit with non-directed edges as a conventional resistor. The directed edges are simulated as at least one of a conventional resistor coupled with a forward-biased ideal diode in direction of the directed edges. The temporal edges are simulated with a time-delay circuit involving, at least in part, a capacitor. Further, relatedness between all pairs of nodes is calculated in accordance with the rules of electrical circuit topology.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: September 19, 2017
    Assignee: CRAYON DATA PTE. LTD
    Inventors: Ajay Kashyap, Sundara Raghavan Sankaran
  • Publication number: 20160246901
    Abstract: Methods and systems for measuring relatedness, known as net affinity, between any two arbitrary nodes, known as entities, in a graph is provided. According to one embodiment, unprocessed data about entities is collected from various data sources. The unprocessed data is transformed to a graph with entities as nodes and corresponding direct affinities between them as edges. Depending on relationship between corresponding nodes, the corresponding edges are at least one of non-directed, directed and temporal. The graph is simulated as an electrical circuit with non-directed edges as a conventional resistor. The directed edges are simulated as at least one of a conventional resistor coupled with a forward-biased ideal diode in direction of the directed edges. The temporal edges are simulated with a time-delay circuit involving, at least in part, a capacitor. Further, relatedness between all pairs of nodes is calculated in accordance with the rules of electrical circuit topology.
    Type: Application
    Filed: February 27, 2015
    Publication date: August 25, 2016
    Inventors: AJAY KASHYAP, SUNDARA RAGHAVAN SANKARAN