Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for improving the performance of a front side bus using an early defer-reply mechanism. In some embodiments, an integrated circuit receives a memory read request and accesses memory to obtain read data responsive to receiving the memory read request. The integrated circuit may initiate a defer-reply transaction corresponding to the memory read request N front side bus (FSB) clocks prior to receiving the read data from the memory.

Abstract: In an embodiment, a method is provided. The method of this embodiment provides receiving a request for data from a processor of a plurality of processors, determining a cache entry location based, at least in part, on the request, storing the data in a cache corresponding to the processor at the cache entry location, and storing a coherency record corresponding to the data in an affinity corresponding to the cache.

Abstract: The method of the present invention provides a procedure for testing shared-memory multi-processor (SMMP) performance by formulating and modifying a given memory contention matrix (MCM), which is generated by collecting traces of memory addresses accessed by so-called subcalls in an SMMPCC. A subcall pair contending for at least one shared memory access address enters a "1" at the respective matrix element. For subcall pairs not sharing any memory address a ".O slashed." is entered.