Abstract: A cooling device for attachment to a helmet includes a fan and an electronics assembly. The fan is operable to draw external air into the cooling device. The electronics assembly is operable to control the rotation speed of the fan based on a speed of movement of a user wearing the helmet with the cooling device attached to the helmet. The cooling device additionally includes an air filter, and a deflector to direct cooled air to a desired one of different regions inside the helmet.

Abstract: A cooling device for attachment to a helmet includes a fan and an electronics assembly. The fan is operable to draw external air into the cooling device. The electronics assembly is operable to control the rotation speed of the fan based on a speed of movement of a user wearing the helmet with the cooling device attached to the helmet. The cooling device additionally includes an air filter, and a deflector to direct cooled air to a desired one of different regions inside the helmet.

Abstract: A headgear for protecting a user from head injury includes a helmet and a cooling unit. The cooling unit is designed to be attachable to, and detachable from, the helmet by the user during normal use of the headgear. In an embodiment, the cooling unit includes one or more inlets, a fan for drawing in air into the cooling unit via the one or more inlets, a pad to hold moisture to cool the air drawn into the cooling unit to generate cooled air, and an air outlet to direct the cooled air into said helmet.

Abstract: A helmet with a mechanism for cooling comprises an inlet for allowing external air to flow into air pathways in the helmet, and a pad to hold moisture (liquid) to cool the air after the air has entered the helmet via the inlet. The helmet also contains a reservoir to hold the liquid, and a channel from the reservoir to the pad to transfer the liquid for providing moisture to the pad. Flowing air, cooled by the moistened pad, provides cooling to the wearer of the helmet.

Abstract: A headgear for protecting a user from head injury includes a helmet and a cooling unit. The cooling unit is designed to be attachable to, and detachable from, the helmet by the user during normal use of the headgear. In an embodiment, the cooling unit includes one or more inlets, a fan for drawing in air into the cooling unit via the one or more inlets, a pad to hold moisture to cool the air drawn into the cooling unit to generate cooled air, and an air outlet to direct the cooled air into said helmet.

Abstract: A helmet with a mechanism for cooling comprises an inlet for allowing external air to flow into air pathways in the helmet, and a pad to hold moisture (liquid) to cool the air after the air has entered the helmet via the inlet. The helmet also contains a reservoir to hold the liquid, and a channel from the reservoir to the pad to transfer the liquid for providing moisture to the pad. Flowing air, cooled by the moistened pad, provides cooling to the wearer of the helmet.

Abstract: A circuit for reducing flicker noise includes a first current source coupled to an input current. The circuit includes current minors to generate output currents in response to the input current. The output currents include the flicker noise. In addition, the circuit includes a chopping circuit to reduce the flicker noise from each of the output currents.

Abstract: A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.

Abstract: A Delay Locked Loop (DLL) and method for generating multiple equally spaced phases over a wide frequency range is disclosed. The DLL includes a delay line, and a control module. The delay line receives a reference clock signal and outputs a final delay clock signal in response to the reference clock signal. The delay line includes a plurality of delay cells connected in series. The plurality of delay cells generate a plurality of delay clock signals having equally spaced phases. The control module generates a phase control signal based on counting a number of pulses of the reference clock signal that are input to the delay line before occurrence of a first corresponding pulse of the final delay clock signal.

Abstract: A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.

Abstract: Methods and systems for input voltage droop compensation in video/graphics front-end systems. The method of an embodiment of the invention captures input voltage information supplied to an Analog-to-Digital Converter (ADC) operatively coupled to a bypass capacitor in a video/graphics front-end system; calculates a droop in the input voltage in ADC due to a charge sharing between an input sampling capacitor of the ADC and the bypass capacitor; and compensates for the value of the bypass capacitor using an output of the ADC. Embodiments of the invention provide an improved freedom in the choice of off-chip bypass capacitance in video/graphics front-end systems.

Abstract: A delay line including a sequence of identical delay cells with improved gain and in built duty cycle distortion control and a method thereof is disclosed. Each delay cell of the sequence includes a current source, four transistors, and a load capacitor. A gate of the current source receives a voltage bias that controls a delay of the delay cell. A drain of the first transistor is connected to the drain of the current source. The first and second transistor gates receive an input clock signal. The second transistor drain is connected to the source of the current source. The third transistor gate and the load capacitor are also connected to the drain of the current source. The fourth transistor drain is connected to the third transistor drain. The fourth transistor gate is coupled to an output of a second consecutive delay cell for duty cycle distortion control.

Abstract: A system and method for improving the dynamic performance in an analog-to-digital converter (ADC) by randomizing the differential mismatch. The differential mismatch in an input analog signal is randomized by flipping the input signal and output signal randomly.

Abstract: A delay line including a sequence of identical delay cells with improved gain and in built duty cycle distortion control and a method thereof is disclosed. Each delay cell of the sequence includes a current source, four transistors, and a load capacitor. A gate of the current source receives a voltage bias that controls a delay of the delay cell. A drain of the first transistor is connected to the drain of the current source. The first and second transistor gates receive an input clock signal. The second transistor drain is connected to the source of the current source. The third transistor gate and the load capacitor are also connected to the drain of the current source. The fourth transistor drain is connected to the third transistor drain. The fourth transistor gate is coupled to an output of a second consecutive delay cell for duty cycle distortion control.

Abstract: Methods and systems for input voltage droop compensation in video/graphics front-end systems. The method of an embodiment of the invention captures input voltage information supplied to an Analog-to-Digital Converter (ADC) operatively coupled to a bypass capacitor in a video/graphics front-end system; calculates a droop in the input voltage in ADC due to a charge sharing between an input sampling capacitor of the ADC and the bypass capacitor; and compensates for the value of the bypass capacitor using an output of the ADC. Embodiments of the invention provide an improved freedom in the choice of off-chip bypass capacitance in video/graphics front-end systems.

Abstract: A Delay Locked Loop (DLL) and method for generating multiple equally spaced phases over a wide frequency range is disclosed. The DLL includes a delay line, and a control module. The delay line receives a reference clock signal and outputs a final delay clock signal in response to the reference clock signal. The delay line includes a plurality of delay cells connected in series. The plurality of delay cells generate a plurality of delay clock signals having equally spaced phases. The control module generates a phase control signal based on counting a number of pulses of the reference clock signal that are input to the delay line before occurrence of a first corresponding pulse of the final delay clock signal.

Abstract: A system and method for improving the dynamic performance in an analog-to-digital converter (ADC) by randomizing the differential mismatch. The differential mismatch in an input analog signal is randomized by flipping the input signal and output signal randomly.

Abstract: A transceiver which effectively cancels interference caused by a component (e.g., driver) of a transmitter (contained in the transceiver). The input and output signals of the component are examined to estimate the magnitude of the interference, and the interference is canceled according to the estimate. Accordingly, the component need not be implemented with high accuracy/precision.