Patents by Inventor Sundararajan Ranganathan

Sundararajan Ranganathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and apparatus for congestion-aware buffering using voltage isolation pathways for integrated circuit designs with multi-power domains
    Patent number: 9190358
    Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: November 17, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Sundararajan Ranganathan, Paras Gupta, Raghavendra Dasegowda, Rajesh Verma, Parissa Najdesamii
  • METHODS AND APPARATUS FOR CONGESTION-AWARE BUFFERING USING VOLTAGE ISOLATION PATHWAYS FOR INTEGRATED CIRCUIT DESIGNS WITH MULTI-POWER DOMAINS
    Publication number: 20140374873
    Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.
    Type: Application
    Filed: September 12, 2014
    Publication date: December 25, 2014
    Inventors: Sundararajan Ranganathan, Paras Gupta, Raghavendra Dasegowda, Rajesh Verma, Parissa Najdesamii
  • Methods and apparatus for congestion-aware buffering using voltage isolation pathways for integrated circuit designs with multi-power domains
    Patent number: 8853815
    Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 7, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Sundararajan Ranganathan, Paras Gupta, Raghavendra Dasegowda, Rajesh Verma, Parissa Najdesamii
  • METHODS AND APPARATUS FOR CONGESTION-AWARE BUFFERING USING VOLTAGE ISOLATION PATHWAYS FOR INTEGRATED CIRCUIT DESIGNS WITH MULTI-POWER DOMAINS
    Publication number: 20140264715
    Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Sundararajan Ranganathan, Paras Gupta, Raghavendra Dasegowda, Rajesh Verma, Parissa Najdesamii