Patents by Inventor Sundararajan Sankaranarayanan

Sundararajan Sankaranarayanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9620202
    Abstract: Channel information and channel conditions that are determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is adjusted with that precision.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: April 11, 2017
    Assignee: Seagate Technology LLC
    Inventors: Zhengang Chen, Erich F. Haratsch, Sundararajan Sankaranarayanan
  • Patent number: 9563502
    Abstract: Methods and apparatus are provided for read retry operations with read reference voltages ranked for different page populations of a memory. One method comprises obtaining a plurality of rankings of a plurality of read reference voltages for a plurality of page populations, wherein the rankings are based on a predefined performance metric; and reading a codeword from the memory a plurality of times, wherein each of the read operations uses a different one of the plurality of read reference voltages selected based on the rankings of the plurality of read reference voltages. The performance metric comprises, for example, a bit error rate, a bit polarity disparity, a substantially minimal syndrome weight and/or measures of an average system latency or a tail latency. The ranking is optionally based on a size of the page populations that had each of the ranked read reference voltages. Channel estimation is performed separately for each of the plurality of page populations.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: February 7, 2017
    Assignee: Seagate Technology LLC
    Inventors: AbdelHakim S. Alhussien, Sundararajan Sankaranarayanan, Thuy Van Nguyen, Ludovic Danjean, Erich F. Haratsch
  • Patent number: 9548128
    Abstract: An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: January 17, 2017
    Assignee: Seagate Technology LLC
    Inventors: AbdelHakim S Alhussien, Erich F Haratsch, Sundararajan Sankaranarayanan, YingQuan Wu
  • Patent number: 9455004
    Abstract: An apparatus having a circuit and a decoder is disclosed. The circuit is configured to adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting the initial reference voltage an amount toward a center of a window and read a codeword from the memory a number of times. The window bounds a sweep of the reference voltages. Each retry of the reads uses a respective reference voltage from a pattern of the reference voltages. The pattern is symmetrically spaced about the initial reference voltage. The pattern fits in the window. The decoder is configured to generate read data by performing an iterative decoding procedure on the codeword based on the reads.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: September 27, 2016
    Assignee: Seagate Technology LLC
    Inventors: AbdelHakim S. Alhussien, Yunxiang Wu, Sundararajan Sankaranarayanan, Zhengang Chen, Erich F. Haratsch
  • Patent number: 9417797
    Abstract: An adaptive channel tracking algorithm performed by a flash memory system obtains disparity metrics and derivative metrics and uses a combination of the disparity and derivative metrics to estimate an optimal read reference voltage. The estimation of the optimal read reference voltage does not rely on assumptions about the underlying cell voltage distributions and results in a good estimate of the read reference voltage even if the standard deviations of the cell voltage distributions are different. In addition, the algorithm is relatively simple and less computationally intensive to perform than the known tracking algorithms.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: August 16, 2016
    Assignee: Seagate Technology LLC
    Inventors: Zhengang Chen, Erich F. Haratsch, Sundararajan Sankaranarayanan, Yunxiang Wu
  • Patent number: 9396792
    Abstract: An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) perform one or more attempts of a soft-decision decode of data stored in the nonvolatile memory, where soft-decision decode uses a plurality of log likelihood ratio values stored in a table, (ii) generate one or more adjusted log likelihood ratio values by adding a constant value to one or more of the log likelihood ratio values in response to a failure to decode the data using the log likelihood ratio values and (iii) re-decode the data using the adjusted log likelihood ratio values.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: July 19, 2016
    Assignee: Seagate Technology LLC
    Inventors: Yunxiang Wu, Zhengang Chen, AbdelHakim S. Alhussien, Sundararajan Sankaranarayanan, Erich F. Haratsch
  • Publication number: 20160118093
    Abstract: An apparatus having a circuit and a decoder is disclosed. The circuit is configured to adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting the initial reference voltage an amount toward a center of a window and read a codeword from the memory a number of times. The window bounds a sweep of the reference voltages. Each retry of the reads uses a respective reference voltage from a pattern of the reference voltages. The pattern is symmetrically spaced about the initial reference voltage. The pattern fits in the window. The decoder is configured to generate read data by performing an iterative decoding procedure on the codeword based on the reads.
    Type: Application
    Filed: January 7, 2016
    Publication date: April 28, 2016
    Inventors: AbdelHakim S. Alhussien, Yunxiang Wu, Sundararajan Sankaranarayanan, Zhengang Chen, Erich F. Haratsch
  • Publication number: 20160093396
    Abstract: An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns.
    Type: Application
    Filed: December 7, 2015
    Publication date: March 31, 2016
    Applicant: Seagate Technology LLC
    Inventors: AbdelHakim S Alhussien, Erich F Haratsch, Sundararajan Sankaranarayanan, YingQuan Wu
  • Patent number: 9236099
    Abstract: An apparatus having a circuit and a decoder is disclosed. The circuit is configured to (i) adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting the initial reference voltage an amount toward a center of a window and (ii) read a codeword from the memory a number of times. The window bounds a sweep of the reference voltages. Each retry of the reads uses a respective reference voltage from a pattern of the reference voltages. The pattern is symmetrically spaced about the initial reference voltage. The pattern fits in the window. The decoder is configured to generate read data by performing an iterative decoding procedure on the codeword based on the reads.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: January 12, 2016
    Assignee: Seagate Technology LLC
    Inventors: AbdelHakim S. Alhussien, Yunxiang Wu, Sundararajan Sankaranarayanan, Zhengang Chen, Erich F. Haratsch
  • Publication number: 20150355838
    Abstract: An adaptive channel tracking algorithm performed by a flash memory system obtains disparity metrics and derivative metrics and uses a combination of the disparity and derivative metrics to estimate an optimal read reference voltage. The estimation of the optimal read reference voltage does not rely on assumptions about the underlying cell voltage distributions and results in a good estimate of the read reference voltage even if the standard deviations of the cell voltage distributions are different. In addition, the algorithm is relatively simple and less computationally intensive to perform than the known tracking algorithms.
    Type: Application
    Filed: June 9, 2014
    Publication date: December 10, 2015
    Inventors: Zhengang Chen, Erich F. Haratsch, Sundararajan Sankaranarayanan, Yunxiang Wu
  • Patent number: 9209835
    Abstract: An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: December 8, 2015
    Assignee: Seagate Technology LLC
    Inventors: AbdelHakim S. Alhussien, Erich F. Haratsch, Sundararajan Sankaranarayanan, YingQuan Wu
  • Patent number: 9184954
    Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for perturbing soft data in a layered decoder system.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: November 10, 2015
    Assignee: Seagate Technology LLC
    Inventors: Abdel Hakim S. Alhussien, Ludovik Danjean, Sundararajan Sankaranarayanan, Erich F. Haratsch
  • Patent number: 9165597
    Abstract: Apparatus and method for recovering data from a multi-channel input signal, such as but not limited to a readback signal from a bit patterned medium (BPM) having a plurality of subtracks. In accordance with some embodiments, a single input single output (SISO) equalizer is adapted to generate equalized outputs responsive to alternating subchannels of the multi-channel input signal. A detector is adapted to generate estimates of data symbols represented by the input signal responsive to the equalized outputs. A switching circuit is adapted to switch in different equalizer coefficients for use by the SISO equalizer for each of the alternating subchannels in the input signal.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: October 20, 2015
    Assignee: Seagate Technology LLC
    Inventors: Sundararajan Sankaranarayanan, Raman Venkataramani, Rishi Ahuja
  • Patent number: 9123356
    Abstract: Detecting track information involves receiving first and second overlapping track signals from first and second read elements that read first and second tracks from a data storage medium. Information of the first and second tracks is estimated using the respective first and second track signals. An improved information estimate of the first track is obtained using the first track signal and the estimated information of the second track, and an improved information estimate of the second track is obtained using the second track signal and the estimated information of the first track. First and second track data are decoded using the respective improved information estimates of the first and second tracks.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: September 1, 2015
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Sundararajan Sankaranarayanan, Raman Venkataranmani, William Michael Radich
  • Publication number: 20150243363
    Abstract: An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) perform one or more attempts of a soft-decision decode of data stored in the nonvolatile memory, where soft-decision decode uses a plurality of log likelihood ratio values stored in a table, (ii) generate one or more adjusted log likelihood ratio values by adding a constant value to one or more of the log likelihood ratio values in response to a failure to decode the data using the log likelihood ratio values and (iii) re-decode the data using the adjusted log likelihood ratio values.
    Type: Application
    Filed: March 3, 2014
    Publication date: August 27, 2015
    Applicant: LSI Corporation
    Inventors: Yunxiang Wu, Zhengang Chen, AbdelHakim S. Alhussien, Sundararajan Sankaranarayanan, Erich F. Haratsch
  • Publication number: 20150236726
    Abstract: A data processing system includes a likelihood input operable to receive encoded data, a decoder operable to apply a decoding algorithm to likelihood values for the received encoded data and to yield a decoded output, and a decoder input initialization circuit operable to generate new decoder input values based in part on the likelihood values for the received encoded data after the likelihood values for the received encoded data have failed to converge in the decoder.
    Type: Application
    Filed: March 18, 2014
    Publication date: August 20, 2015
    Applicant: LSI Corporation
    Inventors: Sundararajan Sankaranarayanan, AbdelHakim S. Alhussien, Erich F. Haratsch, Earl Cohen
  • Publication number: 20150199149
    Abstract: An apparatus includes a plurality of memory devices and a controller. The controller is coupled to the plurality of memory devices and configured to store data in the plurality of memory devices using units of super-blocks. Each super-block comprises a block from each of the plurality of memory devices and the controller balances time efficiency and robustness during collection of statistics from soft reads of each super-block.
    Type: Application
    Filed: February 17, 2014
    Publication date: July 16, 2015
    Applicant: LSI Corporation
    Inventors: Sundararajan Sankaranarayanan, Erich F. Haratsch
  • Publication number: 20150162057
    Abstract: An apparatus having a circuit and a decoder is disclosed. The circuit is configured to (i) adjust an initial one of a plurality of reference voltages in a read channel of a memory by shifting the initial reference voltage an amount toward a center of a window and (ii) read a codeword from the memory a number of times. The window bounds a sweep of the reference voltages. Each retry of the reads uses a respective reference voltage from a pattern of the reference voltages. The pattern is symmetrically spaced about the initial reference voltage. The pattern fits in the window. The decoder is configured to generate read data by performing an iterative decoding procedure on the codeword based on the reads.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 11, 2015
    Applicant: LSI Corporation
    Inventors: AbdelHakim S. Alhussien, Yunxiang Wu, Sundararajan Sankaranarayanan, Zhengang Chen, Erich F. Haratsch
  • Publication number: 20150149840
    Abstract: An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns.
    Type: Application
    Filed: December 20, 2013
    Publication date: May 28, 2015
    Applicant: LSI Corporation
    Inventors: AbdelHakim S. Alhussien, Erich F. Haratsch, Sundararajan Sankaranarayanan, YingQuan Wu
  • Patent number: 9036413
    Abstract: Cross-points of flash memory cell voltage distributions are determined by reading data from a portion of the flash memory two or more times using two or more different candidate reference voltages and determining corresponding decision patterns. The frequency of occurrence of the decision patterns in the data read from the flash memory is used to conceptually construct a histogram. The histogram is used to estimate the cross-points. Employing decision patterns enables multiple cross-point voltages to be determined with a minimum of read operations.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: May 19, 2015
    Assignee: Seagate Technology LLC
    Inventors: Yunxiang Wu, Abdel-Hakim Alhussien, Zhengang Chen, Sundararajan Sankaranarayanan, Erich F. Haratsch