Abstract: A method of interconnecting blocks of heterogeneous dimensions using a NoC interconnect with sparse mesh topology includes determining a size of a mesh reference grid based on dimensions of the chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required for each of the blocks of heterogeneous dimensions, overlaying the blocks of heterogeneous dimensions on the mesh reference grid based on based on a guidance floor plan for placement of the blocks of heterogeneous dimensions, removing ones of a plurality of nodes and corresponding ones of links to the ones of the plurality of nodes which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions, and mapping inter-block communication of the network-on-chip architecture over remaining ones of the nodes and corresponding remaining ones of the links.

Abstract: Systems and methods involving construction of a system interconnect in which different channels have different widths in numbers of bits. Example processes to construct such a heterogeneous channel NoC interconnect are disclosed herein, wherein the channel width may be determined based upon the provided specification of bandwidth and latency between various components of the system.

Abstract: Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example embodiments described herein involve deadlock detection during the mapping of user specified communication pattern amongst blocks of the system. Detected deadlocks are then avoided by re-allocation of channel resources. An example embodiment of the deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips.

Abstract: A method of interconnecting blocks of heterogeneous dimensions using a NoC interconnect with sparse mesh topology includes determining a size of a mesh reference grid based on dimensions of the chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required for each of the blocks of heterogeneous dimensions, overlaying the blocks of heterogeneous dimensions on the mesh reference grid based on based on a guidance floor plan for placement of the blocks of heterogeneous dimensions, removing ones of a plurality of nodes and corresponding ones of links to the ones of the plurality of nodes which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions, and mapping inter-block communication of the network-on-chip architecture over remaining ones of the nodes and corresponding remaining ones of the links.

Abstract: A variable frequency clock generator provides complementary phase clock signals for a microprocessor at a selectable one of a plurality of frequencies. The outputs may be dynamically switched between any of the frequencies so that every cycle of the phase clock signals has a duration at least as great as the cycle duration of the highest frequency.

Abstract: Timing signals governing the precharge and evaluation phases of a PLA are generated by internal circuitry so that the PLA can be maintained in a fully static mode without destroying data integrity and without dissipating a significant amount of power. "Dummy" lines connected at every programmable intersection are added to the PLA to provide a measure of the maximum propagation delay. The evaluation phase of the PLA is terminated closely following the maximum propagation delay and precharging is begun soon thereafter. The timing ensures that evaluation completes, valid data is latched and the PLA is returned to a precharge condition even if the phase clock signals are suspended and regardless of the states of the phase clock signals when suspended.