Abstract: A radio-frequency (RF) sampling transmitter (e.g., of the type that may be used in 5G wireless base stations) includes a complex baseband digital-to-analog converter (DAC) response compensator that operates on a complex baseband signal at a sampling rate lower than the sampling rate of an RF sampling DAC in the RF sampling transmitter. The DAC response compensator flattens the sample-and-hold response of the RF sampling DAC only in the passband of interest, addressing the problem of a sin c response introduced by the sample-and-hold operation of the RF sampling DAC and avoiding the architectural complexity and high power consumption of an inverse sin c filter that operates on the signal at a point in the signal chain after it has already been up-converted to an RF passband.

Abstract: A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.

Abstract: A system for generating secondary clock signals from a primary clock signal includes a dithered clock divider which has a first input adapted to receive the primary clock signal and a second input adapted to receive a random division ratio. The dithered clock divider provides a dithered clock signal. The system includes a multi-phase clock generator which has a first input adapted to receive the primary clock signal, a second input adapted to receive the dithered clock signal, and a third input adapted to receive a pseudo-random pattern. The multi-phase clock generator provides the secondary clock signals from multiple phases of the dithered clock signal. The system includes a pseuodo-random pattern generator which provides the pseudo-random pattern.

Abstract: A system for generating secondary clock signals from a primary clock signal includes a dithered clock divider which has a first input adapted to receive the primary clock signal and a second input adapted to receive a random division ratio. The dithered clock divider provides a dithered clock signal. The system includes a multi-phase clock generator which has a first input adapted to receive the primary clock signal, a second input adapted to receive the dithered clock signal, and a third input adapted to receive a pseudo-random pattern. The multi-phase clock generator provides the secondary clock signals from multiple phases of the dithered clock signal. The system includes a pseudo-random pattern generator which provides the pseudo-random pattern.

Abstract: A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.

Abstract: A technique for reinitializing a coupled circuit, the technique including receiving a common configuration value associated with states of a coupled circuit, tracking states associated with the coupled circuit while the coupled circuit is in a low power state based on the common configuration value, receiving the tracked state associated with the coupled circuit, receiving a scaling value associated with the coupled circuit, determining a current state of the coupled circuit based on the tracked state and the scaling value, and transmitting an indication of the current state to the coupled circuit when the coupled circuit has exited the low power state.

Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.

Abstract: A circuit includes a test circuit in an integrated circuit to test signal timing of a logic circuit under test in the integrated circuit. The signal timing includes timing measurements to determine if an output of the logic circuit under test changes state in response to a clock signal. The test circuit includes a bit register that specifies which bits of the logic circuit under test are to be tested in response to the clock signal. A configuration register specifies a selected clock source setting from multiple clock source settings corresponding to a signal speed. The selected clock source is employed to perform the timing measurements of the specified bits of the bit register.

Abstract: A radio-frequency (RF) sampling transmitter (e.g., of the type that may be used in 5G wireless base stations) includes a complex baseband digital-to-analog converter (DAC) response compensator that operates on a complex baseband signal at a sampling rate lower than the sampling rate of an RF sampling DAC in the RF sampling transmitter. The DAC response compensator flattens the sample-and-hold response of the RF sampling DAC only in the passband of interest, addressing the problem of a sin c response introduced by the sample-and-hold operation of the RF sampling DAC and avoiding the architectural complexity and high power consumption of an inverse sin c filter that operates on the signal at a point in the signal chain after it has already been up-converted to an RF passband.

Abstract: One example includes a clock receiver system. The system includes a scan clock generator configured to receive a shift clock signal and a high-speed clock signal and to generate a scan clock signal for a transition fault test (TFT) based on the high-speed clock signal. The scan clock generator can provide the scan clock signal as having a pulse sequence comprising at least one preliminary pulse followed by periodic logic state transitions in a capture window during the TFT. The system also includes receiver logic configured to receive the scan clock signal and being programmed to identify each of the at least one preliminary pulse and the periodic logic state transitions in the capture window to pass the TFT.

Abstract: A radio-frequency (RF) sampling transmitter (e.g., of the type that may be used in 5G wireless base stations) includes a complex baseband digital-to-analog converter (DAC) response compensator that operates on a complex baseband signal at a sampling rate lower than the sampling rate of an RF sampling DAC in the RF sampling transmitter. The DAC response compensator flattens the sample-and-hold response of the RF sampling DAC only in the passband of interest, addressing the problem of a sinc response introduced by the sample-and-hold operation of the RF sampling DAC and avoiding the architectural complexity and high power consumption of an inverse sinc filter that operates on the signal at a point in the signal chain after it has already been up-converted to an RF passband.

Abstract: An electrical system includes a transceiver with an IQ estimator and an IQ mismatch corrector. The electrical system also includes an antenna coupled to the transceiver. The IQ estimator is configured to perform frequency-domain IQ mismatch analysis to determine an IQ mismatch estimate at available frequency bins of a baseband data signal. The IQ mismatch corrector is configured to correct the baseband data signal based on the IQ mismatch estimate.

Abstract: One example includes a clock receiver system. The system includes a scan clock generator configured to receive a shift clock signal and a high-speed clock signal and to generate a scan clock signal for a transition fault test (TFT) based on the high-speed clock signal. The scan clock generator can provide the scan clock signal as having a pulse sequence comprising at least one preliminary pulse followed by periodic logic state transitions in a capture window during the TFT. The system also includes receiver logic configured to receive the scan clock signal and being programmed to identify each of the at least one preliminary pulse and the periodic logic state transitions in the capture window to pass the TFT.

Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.

Abstract: A radio-frequency (RF) sampling transmitter (e.g., of the type that may be used in 5G wireless base stations) includes a complex baseband digital-to-analog converter (DAC) response compensator that operates on a complex baseband signal at a sampling rate lower than the sampling rate of an RF sampling DAC in the RF sampling transmitter. The DAC response compensator flattens the sample-and-hold response of the RF sampling DAC only in the passband of interest, addressing the problem of a sinc response introduced by the sample-and-hold operation of the RF sampling DAC and avoiding the architectural complexity and high power consumption of an inverse sinc filter that operates on the signal at a point in the signal chain after it has already been up-converted to an RF passband.

Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.

Abstract: A digital clock generator for a digital clock domain interfaced to another clock domain through a FIFO, includes division selector circuitry to provide an input randomizing sequence of clock division factors, selected from a defined set of clock division factors corresponding to a target average clock division, and division arbitration circuitry to generate a drift-corrected randomizing sequence of clock division factors, based at least in part on the input randomizing sequence of clock division factors, and an accumulated drift correction signal. A clock drift control loop generates the accumulated drift correction signal, based at least in part on an accumulated clock drift relative to the target average clock division. Clock generation can be based on randomized division with the drift-corrected randomizing sequence of clock division factors. The drift-corrected randomizing sequence of clock division factors can be generated so that clock drift is bounded based on a FIFO depth.

Abstract: A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.

Abstract: A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.

Abstract: A clock generator circuit includes a clock divider circuit, a clock pulse control circuit, a phase shifter circuit, and a clock multiplexer circuit. The clock divider circuit is configured to generate a divided clock having a frequency that is a programmable fraction of a frequency of an input clock. The clock pulse control circuit is coupled to the clock divider circuit, and is configured to generate a pulse shaped clock that includes a clock burst comprising a programmable number of adjacent cycles of the divided clock. The phase shifter circuit is coupled to the clock control circuit, and is configured to generate a plurality of phase shifted clocks. Each of phase shifted clocks is a differently delayed version of the pulse shaped clock. The clock multiplexer circuit is coupled to the phase shifter circuit, and is configured to selectively route each of the phase shifted clocks to an output terminal.