Abstract: System and method for controlling thread execution via time monitoring circuitry in a processing element. Execution of a thread may be suspended via a thread suspend/resume logic block included in the processing element in response to a received suspend thread instruction. An indication of a wakeup time may be received to a time monitoring circuit (TMC) included in the processing element. Time may be monitored via the TMC using a clock included in the processing element, until the wakeup time obtains.

Abstract: Generating a schedule for a distributed real time system. At least one schedule generator may receive temporal properties from respective timed functions executing on master devices, where each master device is connected to a respective plurality of slave devices. Each master includes one or more timed functions configured to control timing of physical input and/or output operations for the respective plurality of slave devices, and streams between the master device and the respective plurality of slave devices. The schedule generator may receive associations between the timed functions and streams between master devices, and generate respective schedules for the masters based at least in part on the temporal properties and the associations. The respective schedules may be distributed to the master devices, and are useable by the master devices to control execution of the timed functions and the streams between the master devices in real time in a coordinated manner.

Abstract: In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described.

Abstract: In a real-time application, one or more computational tasks execute according to a time schedule and use input data from input devices and/or output data from output devices. One or more of the input devices or output devices may be unscheduled devices that attempt to access the peripheral bus at unscheduled times. Such unscheduled bus access can cause the time schedule to become comprised. Various methods for arbitrating access to the bus to better integrate the bus access with the time schedule followed by the application are described.

Abstract: A method and system for scheduling a time critical task. The system may include a processing unit, a hardware assist scheduler, and a memory coupled to both the processing unit and the hardware assist scheduler. The method may include receiving timing information for executing the time critical task, the time critical task executing program instructions via a thread on a core of a processing unit and scheduling the time critical task based on the received timing information. The method may further include programming a lateness timer, waiting for a wakeup time to obtain and notifying the processing unit of the scheduling. Additionally, the method may include executing, on the core of the processing unit, the time critical task in accordance with the scheduling, monitoring the lateness timer, and asserting a thread execution interrupt in response to the lateness timer expiring, thereby suspending execution of the time critical task.

Abstract: System and method for controlling thread execution via time monitoring circuitry in a processing element. Execution of a thread may be suspended via a thread suspend/resume logic block included in the processing element in response to a received suspend thread instruction. An indication of a wakeup time may be received to a time monitoring circuit (TMC) included in the processing element. Time may be monitored via the TMC using a clock included in the processing element, until the wakeup time obtains.

Abstract: Systems and methods for interoperating between networks. A first network may be configured to operate according to a first real time network protocol and each of one or more second networks may be configured to operate according to respective second real time traffic protocols. A mapping may specify data routing between a plurality of ports and the routing may maintain real time behavior between the first network and the one or more second networks. Additionally, routing information may be inserted in packets routed from the one or more second networks to the first network and removed from packets routed from the first network to the one or more second networks. The packets may be routed, based on the mapping, to distinct queues for the first network and the one or more second networks for processing by an application executing on at least one device.

Abstract: A method and system for scheduling a time critical task. The system may include a processing unit, a hardware assist scheduler, and a memory coupled to both the processing unit and the hardware assist scheduler. The method may include receiving timing information for executing the time critical task, the time critical task executing program instructions via a thread on a core of a processing unit and scheduling the time critical task based on the received timing information. The method may further include programming a lateness timer, waiting for a wakeup time to obtain and notifying the processing unit of the scheduling. Additionally, the method may include executing, on the core of the processing unit, the time critical task in accordance with the scheduling, monitoring the lateness timer, and asserting a thread execution interrupt in response to the lateness timer expiring, thereby suspending execution of the time critical task.

Abstract: Systems and methods for mapping an iterative time-based data acquisition (DAQ) operation to an isochronous data transfer channel of a network. A time-sensitive buffer (TSB) associated with the isochronous data transfer channel of the network may be configured. A data rate clock may and a local buffer may be configured. A functional unit may be configured to initiate continuous performance of the iterative time-based DAQ operation, transfer data to the local buffer, initiate transfer of the data between the local buffer and the TSB at a configured start time, and repeat the transferring and initiating transfer in an iterative manner, thereby transferring data between the local buffer and the TSB. The TSB may be configured to communicate data over the isochronous data transfer channel of the network, thereby mapping the iterative time-based DAQ operation to the isochronous data transfer channel of the network.

Abstract: Operating a programmable controller with a plurality of processors. The programmable controller may utilize a first subset of the plurality of processors for a scanning architecture. The first subset of the plurality of processors may be further subdivided for execution of periodic programs or asynchronous programs. The programmable controller may utilize a second subset of the plurality of processors for a data acquisition architecture. Execution of the different architectures may occur independently and may not introduce significant jitter (e.g., for the scanning architecture) or data loss/response time lag (e.g., for the data acquisition architecture). However, the programmable controller may operate according to any combination of the divisions and/or architectures described herein.

Abstract: Systems and methods for interoperating between networks. A first network may be configured to operate according to a first real time network protocol and each of one or more second networks may be configured to operate according to respective second real time traffic protocols. A mapping may specify data routing between a plurality of ports and the routing may maintain real time behavior between the first network and the one or more second networks. Additionally, routing information may be inserted in packets routed from the one or more second networks to the first network and removed from packets routed from the first network to the one or more second networks. The packets may be routed, based on the mapping, to distinct queues for the first network and the one or more second networks for processing by an application executing on at least one device.

Abstract: System and method for controlling thread execution via time monitoring circuitry in a processing element. Execution of a thread may be suspended via a thread suspend/resume logic block included in the processing element in response to a received suspend thread instruction. An indication of a wakeup time may be received to a time monitoring circuit (TMC) included in the processing element. Time may be monitored via the TMC using a clock included in the processing element, until the wakeup time obtains. The thread suspend/resume logic block included in the processing element may be invoked by the TMC in response to the wakeup time obtaining, thereby resuming execution of the thread.

Abstract: A method for automatically creating a customized motion controller based on user input specifying desired characteristics of the motion controller. The method may compile the program into executable code and download the executable code to a target platform, thus enabling the target platform to function as the specified customized motion controller. User input may specify characteristics of the motion controller system such as: the target platform; the configuration of motors, sensors and I/O devices to be used; the supervisory control functions to be implemented; and the target language for the motion control program.

Abstract: Systems and methods for scheduling data egress using a time-sensitive (TS) network switch. The TS network switch may include a functional unit, a plurality of ports, and a plurality of queues. Each port may be associated with a set of network addresses for TS packets and may be configured with a set of egress periods. Each queue may be associated with a TS packet type and a port. The functional unit may be configured to receive TS packets asynchronously from a network node via a first port, determine a second port for egressing a TS packet, determine an egress period for egressing the TS packet, determine that the TS packet cannot currently be egressed from the second port, queue the TS packet in a first queue, where the first queue is associated with the second port, and egress the TS packet in the respective time window from the second port.

Abstract: System and method for developing a motion application. A motion manager component implementing a supervisory control function and at least one trajectory generation algorithm is stored on a motion controller. A first application programming interface (API) for interfacing the motion manager component to a user developed motion control application is displayed. A second API for interfacing the motion manager component to a user developed communication interface component is displayed. A user application executable for sequencing motion operations in the motion system is created using the first API is created in response to user input. A first communication interface component is created using the second API in response to user input, where the communication interface component is operable to interface with the motion manager component using the second API, and where the user developed communication interface component is executable to communicate with a motion element, e.g., a drive or simulation.

Abstract: Systems and methods for mapping an iterative time-based data acquisition (DAQ) operation to an isochronous data transfer channel of a network. A time-sensitive buffer (TSB) associated with the isochronous data transfer channel of the network may be configured. A data rate clock may and a local buffer may be configured. A functional unit may be configured to initiate continuous performance of the iterative time-based DAQ operation, transfer data to the local buffer, initiate transfer of the data between the local buffer and the TSB at a configured start time, and repeat the transferring and initiating transfer in an iterative manner, thereby transferring data between the local buffer and the TSB. The TSB may be configured to communicate data over the isochronous data transfer channel of the network, thereby mapping the iterative time-based DAQ operation to the isochronous data transfer channel of the network.

Abstract: A method and system for scheduling a time critical task. The system may include a processing unit, a hardware assist scheduler, and a memory coupled to both the processing unit and the hardware assist scheduler. The method may include receiving timing information for executing the time critical task, the time critical task executing program instructions via a thread on a core of a processing unit and scheduling the time critical task based on the received timing information. The method may further include programming a lateness timer, waiting for a wakeup time to obtain and notifying the processing unit of the scheduling. Additionally, the method may include executing, on the core of the processing unit, the time critical task in accordance with the scheduling, monitoring the lateness timer, and asserting a thread execution interrupt in response to the lateness timer expiring, thereby suspending execution of the time critical task.

Abstract: Systems and methods for interoperating between networks. A first network may be configured to operate according to a first real time network protocol and each of one or more second networks may be configured to operate according to respective second real time traffic protocols. A mapping may specify data routing between a plurality of ports and the routing may maintain real time behavior between the first network and the one or more second networks. Additionally, routing information may be inserted in packets routed from the one or more second networks to the first network and removed from packets routed from the first network to the one or more second networks. The packets may be routed, based on the mapping, to distinct queues for the first network and the one or more second networks for processing by an application executing on at least one device.

Abstract: Systems and methods for scheduling data egress using a time-sensitive (TS) network switch. The TS network switch may include a functional unit, a plurality of ports, and a plurality of queues. Each port may be associated with a set of network addresses for TS packets and may be configured with a set of egress periods. Each queue may be associated with a TS packet type and a port. The functional unit may be configured to receive TS packets asynchronously from a network node via a first port, determine a second port for egressing a TS packet, determine an egress period for egressing the TS packet, determine that the TS packet cannot currently be egressed from the second port, queue the TS packet in a first queue, where the first queue is associated with the second port, and egress the TS packet in the respective time window from the second port.

Abstract: Devices and methods for synchronizing devices over a switched fabric. A master device maintains a global time, determines a mapping between the global time and a counter of a switch over a memory-mapped fabric, and sends the mapping to a slave device. A slave device maintains a local time, determines a first mapping between the local time and a counter of a switch, receives a second mapping between the counter and a global time of the master device, and synchronizes its local time to the global time based on the first and second mappings. The master and slave device may map their times to the counter by sending respective request packets to the switch and receiving respective completion packets including respective counter values from the switch. The master and slave device may determine respective time values corresponding to the respective counter values based on in-switch delays of the packets.