Patents by Inventor Sundeep ROY

Sundeep ROY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10437713
    Abstract: A system for equivalence class analysis-based automated requirements-based test case generation includes a control processor, a data store containing textual design requirements, a textual converter unit structured to convert the textual design requirements to a machine-readable version of design requirements, a requirement partition unit configured to partition the machine-readable design requirements into one or more sets of related design requirements, an equivalence class partition unit configured to process the machine-readable design requirements and input/output variables into a set of equivalence classes, an equivalence class analyzer unit structured to analyze the set of equivalence classes to generate equivalence class tests and identify uncovered input space, and a boundary class analyzer unit structured to identify boundaries of the equivalence classes and generate boundary value tests and robustness tests.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: October 8, 2019
    Assignee: General Electric Company
    Inventors: Panagiotis Manolios, Meng Li, Italo Romani De Oliveira, Augusto Marasca De Conto, Han Yu, Daniel Russell, Sundeep Roy
  • Publication number: 20180300226
    Abstract: A system for equivalence class analysis-based automated requirements-based test case generation includes a control processor, a data store containing textual design requirements, a textual converter unit structured to convert the textual design requirements to a machine-readable version of design requirements, a requirement partition unit configured to partition the machine-readable design requirements into one or more sets of related design requirements, an equivalence class partition unit configured to process the machine-readable design requirements and input/output variables into a set of equivalence classes, an equivalence class analyzer unit structured to analyze the set of equivalence classes to generate equivalence class tests and identify uncovered input space, and a boundary class analyzer unit structured to identify boundaries of the equivalence classes and generate boundary value tests and robustness tests.
    Type: Application
    Filed: June 21, 2018
    Publication date: October 18, 2018
    Inventors: Panagiotis MANOLIOS, Meng LI, Italo ROMANI DE OLIVEIRA, Augusto Marasca De CONTO, Han YU, Daniel RUSSELL, Sundeep ROY