Abstract: An apparatus and method for generating a comparand in a content addressable memory array. For one embodiment, the apparatus includes a content addressable memory (CAM) array and translation circuitry. The CAM array receives a comparand and the translation circuitry includes at least one first input, at least one second input, and at least one output. The first input is configured to receive an input data having a plurality of bit groups, wherein a first bit group has a first position in the input data relative to other bit groups. The second input is configured to receive translation information indicative of translation of the first bit group from the first position to a different position in a comparand. The output is coupled to the CAM array to transmit the comparand to the CAM array. For one example, the translation circuitry includes a switch circuit that may include one or more multiplexers or demultiplexers.

Abstract: An apparatus and method for generating a comparand in a content addressable memory array. For one embodiment, the apparatus includes a content addressable memory (CAM) array and translation circuitry. The CAM array receives a comparand and the translation circuitry includes at least one first input, at least one second input, and at least one output. The first input is configured to receive an input data having a plurality of bit groups, wherein a first bit group has a first position in the input data relative to other bit groups. The second input is configured to receive translation information indicative of translation of the first bit group from the first position to a different position in a comparand. The output is coupled to the CAM array to transmit the comparand to the CAM array. For one example, the translation circuitry includes a switch circuit that may include one or more multiplexers or demultiplexers.

Abstract: A scheduling mechanism for satisfying specified Quality of Service (QoS) guarantees for each VC of an end-point host in an ATM network. The scheduling mechanism includes a time slot ring, a VC table and a pending queue. The time slot ring is an array, wherein each element represents a time slot. Each slot contains a pointer which contains the virtual channel identifier (VCID) which is to be serviced in this time slot. The VC table is an array of all the VC descriptors. The pending queue is used for queuing a new VC and also at a later time, when the scheduler is unable to find a time slot for a VC it is queued in the pending queue. The scheduler reads and processes one slot at a time at the maximum speed that the physical link will allow. The scheduler circularly services the slots in the ring continuously and a current slot pointer (CSP) points to the slot being serviced.

Abstract: An apparatus an method for adaptive time slot scheduling of communications traffic generated by end-point host in ATM network. The scheduler includes a time slot ring including an array of time slots, wherein each of said time slots includes a virtual channel identifier (VCID) of a virtual channel (VC) to be serviced; a VC table including an array of VC descriptors, wherein the VCID stored in said time slot ring points to a VC descriptor in the VC table; and processor for scheduling the VCs in said time slots of said time slot ring, wherein the time slots ring are circularly processed in a continuous fashion thereby enabling scheduled transmission of ATM cells in the network. The processor is operable to queue the VCID of a newly calculated target slot in an already occupied time slot if the newly calculated target slot is occupied, thereby creating a linked list of VCs, and the processor is operable to service all VCs at a single time slot before proceeding to a next time slot.