Patents by Inventor Suneui PARK

Suneui PARK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FREQUENCY MULTIPLIER BASED ON RING OSCILLATOR USING POWER GATING INJECTION LOCKING
    Publication number: 20240267037
    Abstract: A frequency multiplier includes a first ring oscillator, a second ring oscillator that is turned on complementarily to the first ring oscillator, a combining circuit that combines a first output signal of the first ring oscillator and a second output signal of the second ring oscillator to generate a final output signal, and a calibration circuit that corrects a discontinuous pulse included in the final output signal based on feedback of the final output signal.
    Type: Application
    Filed: February 2, 2024
    Publication date: August 8, 2024
    Applicants: SAMSUNG ELECTRONICS CO., LTD., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Chanyoung JEONG, Jaehyouk CHOI, Junhyeok YANG, Suneui PARK
  • Ultra-low jitter low-power W/D-band phase-locked loop using power-gating injection-locked frequency multiplierbased phase detector
    Patent number: 11895218
    Abstract: Proposed are an ultra-low jitter low-power phase-locked loop using a power-gating injection-locked frequency multiplier-based phase detector (PG-ILFM PD) and an operating method thereof. The proposed PG-ILFM PD includes a replica voltage controlled oscillator (R-VCO) configured to cut off the power supply of the R-VCO repeatedly based on a reference signal SREF and a fundamental sampling phase detector (FSPD) configured to receive an output signal SILFM of the R-VCO as a reference signal for sampling and detect a phase error of a main voltage controlled oscillator (M-VCO).
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: February 6, 2024
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jaehyouk Choi, Suneui Park, Seyeon Yoo, Seojin Choi, Jooeun Bang
  • ULTRA-LOW JITTER LOW-POWER W/D-BAND PHASE-LOCKED LOOP USING POWER-GATING INJECTION-LOCKED FREQUENCY MULTIPLIERBASED PHASE DETECTOR
    Publication number: 20230224138
    Abstract: Proposed are an ultra-low jitter low-power phase-locked loop using a power-gating injection-locked frequency multiplier-based phase detector (PG-ILFM PD) and an operating method thereof. The proposed PG-ILFM PD includes a replica voltage controlled oscillator (R-VCO) configured to cut off the power supply of the R-VCO repeatedly based on a reference signal SREF and a fundamental sampling phase detector (FSPD) configured to receive an output signal SILFM of the R-VCO as a reference signal for sampling and detect a phase error of a main voltage controlled oscillator (M-VCO).
    Type: Application
    Filed: April 13, 2022
    Publication date: July 13, 2023
    Inventors: Jaehyouk CHOI, Suneui PARK, Seyeon YOO, Seojin CHOI, Jooeun BANG