Abstract: A semiconductor memory apparatus comprises first and second memory blocks each comprising semiconductor elements coupled to first and second local line groups, a first switching circuit configured to couple a first global line group to the first local line group of the first memory block in response to a block selection signal, a second switching circuit configured to couple a second global line group to the second local line groups of the first and second memory blocks in response to the block selection signal, and a third switching circuit configured to couple the first global line group to the first local line group of the second memory block in response to the block selection signal.

Abstract: Disclosed is a cosmetic composition having a double-shell type nano-structure. More particularly, the nano-structure of the cosmetic composition includes: a water-soluble bioactive ingredient core; a core shell containing poly(ethyleneglycol)-poly(caprolactone)-poly(ethyleneglycol) (PE-PCL-PEG) triblock copolymer in order to include the bioactive ingredient core therein; and an outer shell containing phospholipids or derivatives thereof in order to enclose the core shell therein. Such a cosmetic composition improves stability of active components which are prone to oxidation, light degradation, heat degradation, etc., is formed in a nanoparticle size which in turn shows high transdermal absorption and is very useful to prepare a cosmetic composition stably encapsulating various bioactive ingredients with anti-wrinkle effects, whitening effects, and so forth.

Abstract: A cell string included in a memory cell array of a nonvolatile memory device includes a plurality of memory cells, a string select transistor, and a ground select transistor. The plurality of memory cells are connected in series. The string select transistor is connected between a bitline and the plurality of memory cells, and has a structure substantially the same as a structure of each memory cell. The ground select transistor is connected between the plurality of memory cells and a common source line, and has a structure substantially the same as the structure of each memory cell.

Abstract: A semiconductor memory apparatus comprises first and second memory blocks each comprising semiconductor elements coupled to first and second local line groups, a first switching circuit configured to couple a first global line group to the first local line group of the first memory block in response to a block selection signal, a second switching circuit configured to couple a second global line group to the second local line groups of the first and second memory blocks in response to the block selection signal, and a third switching circuit configured to couple the first global line group to the first local line group of the second memory block in response to the block selection signal.

Abstract: Disclosed are a contact plug in a semiconductor device and method of forming the same. After a junction region where a contact plug is formed upwardly up to the bottom of a metal wire, the raised junction region and the metal wire are connected by a contact plug. Or after a first contact plug of the same area is formed on the junction region up to the bottom of the metal wires, the first contact plug is connected by a second contact plug. Thus, the width of the contact plug except for some portions is increased by maximum. It is thus possible to prevent an electric field from being concentrated and prohibit on-current from reduced, thus improving the electrical properties of devices.

Abstract: The disclosed is a method of programming a flash memory cell, comprising; a step of an over-programming of a flash memory cell to-be-programmed; a first recovering step of the over-programmed flash memory cell by adjusting a gate bias of the flash memory cell; a second recovering step of the over-programmed flash memory cell by setting the gate bias to a voltage of 0V and then adjusting a bulk bias of the over-programmed flash memory cell; a third recovering step of the over-programmed flash memory cell by floating the gate bias and then adjusting the bulk bias of the over-programmed flash memory cell; and a fourth recovering step of the over-programmed flash memory cell by adjusting the bulk bias of the over-programmed flash memory cell using a self-boosting operation.

Abstract: The disclosed is a method of programming a flash memory cell, comprising; a step of an over-programming of a flash memory cell to-be-programmed; a first recovering step of the over-programmed flash memory cell by adjusting a gate bias of the flash memory cell; a second recovering step of the over-programmed flash memory cell by setting the gate bias to a voltage of 0V and then adjusting a bulk bias of the over-programmed flash memory cell; a third recovering step of the over-programmed flash memory cell by floating the gate bias and then adjusting the bulk bias of the over-programmed flash memory cell; and a fourth recovering step of the over-programmed flash memory cell by adjusting the bulk bias of the over-programmed flash memory cell using a self-boosting operation.