Abstract: A method of planarizing a substrate employs two separate chemical mechanical polishing (CMP) steps. In the first CMP step, the substrate is polished using a first CMP slurry solution and a polishing pad. A diluting solution is then applied to the polishing pad to remove slurry of the first CMP step. In the second CMP step, after applying the diluting solution to the polishing pad to remove the first slurry, second CMP slurry solution is applied to the polishing pad to facilitate additional planarization of the substrate. In a particular embodiment of this invention, the diluting solution comprises a buffer solution having a pH level corresponding to a pH level of one of the first or second CMP slurry solution. In accordance with another aspect of this embodiment, a plurality of different diluting solutions are applied to the polishing pad intermediate the respective first and second CMP steps.

Abstract: A method of planarizing a substrate employs two separate chemical mechanical polishing (CMP) steps. In the first CMP step, the substrate is polished using a first CMP slurry solution and a polishing pad. A diluting solution is then applied to the polishing pad to remove slurry of the first CMP step. In the second CMP step, after applying the diluting solution to the polishing pad to remove the first slurry, second CMP slurry solution is applied to the polishing pad to facilitate additional planarization of the substrate. In a particular embodiment of this invention, the diluting solution comprises a buffer solution having a pH level corresponding to a pH level of one of the first or second CMP slurry solution. In accordance with another aspect of this embodiment, a plurality of different diluting solutions are applied to the polishing pad intermediate the respective first and second CMP steps.

Abstract: A process of polishing two dissimilar conductive materials deposited on semiconductor device substrate optimizes the polishing of each of the conductive material independently, while utilizing the same polishing equipment for manufacturing efficiency. A tungsten layer (258) and a titanium layer (256) of a semiconductor device substrate (250) are polished using one polisher (10) but two different slurry formulations. The two slurries can be dispensed sequentially onto the same polishing platen (132) from two different urce containers (111 and 112), wherein the first slurry is dispensed until e tungsten is removed and then the slurry dispense is switched to second slurry for removal of the titanium. In a preferred embodiment, the first slurry composition is a ferric nitrate slurry while the second slurry composition is an oxalic acid slurry.

Abstract: A method of planarizing a substrate employs two separate chemical mechanical polishing (CMP) steps. In the first CMP step, the substrate is polished using a first CMP slurry solution and a polishing pad. A diluting solution is then applied to the polishing pad to remove slurry of the first CMP step. In the second CMP step, after applying the diluting solution to the polishing pad to remove the first slurry, second CMP slurry solution is applied to the polishing pad to facilitate additional planarization of the substrate. In a particular embodiment of this invention, the diluting solution comprises a buffer solution having a pH level corresponding to a pH level of one of the first or second CMP slurry solution. In accordance with another aspect of this embodiment, a plurality of different diluting solutions are applied to the polishing pad intermediate the respective first and second CMP steps.

Abstract: A process of polishing two dissimilar conductive materials deposited on semiconductor device substrate optimizes the polishing of each of the conductive material independently, while utilizing the same polishing equipment for manufacturing efficiency. A tungsten layer (258) and a titanium layer (256) of a semiconductor device substrate (250) are polished using one polisher (10) but two different slurry formulations. The two slurries can be dispensed sequentially onto the same polishing platen (132) from two different source containers (111 and 112), wherein the first slurry is dispensed until the tungsten is removed and then the slurry dispense is switched to the second slurry for removal of the titanium. In a preferred embodiment, the first slurry composition is a ferric nitrate slurry while the second slurry composition is an oxalic acid slurry.

Abstract: A process for conditioning a polishing pad has been developed that incorporates in-situ conditioning where the conditioning is performed while the substrate (27, 40) is on the polishing pad (22) but terminates before the polishing of the substrate (27, 40) is completed. In one embodiment, ex-situ conditioning of the polishing pad (22) is used on the polishing pad between substrates (27, 40). The process has benefits of both in-situ and ex-situ conditioning.

Abstract: A method of planarizing a substrate employs two separate chemical mechanical polishing (CMP) steps. In the first CMP step, the substrate is polished using a first CMP slurry solution and a polishing pad. A diluting solution is then applied to the polishing pad to remove slurry of the first CMP step. In the second CMP step, after applying the diluting solution to the polishing pad to remove the first slurry, second CMP slurry solution is applied to the polishing pad to facilitate additional planarization of the substrate. In a particular embodiment of this invention, the diluting solution comprises a buffer solution having a pH level corresponding to a pH level of one of the first or second CMP slurry solution. In accordance with another aspect of this embodiment, a plurality of different diluting solutions are applied to the polishing pad intermediate the respective first and second CMP steps.

Abstract: A polishing pad (34) with a poromeric structure polishes two dissimilar materials (56, 58). By using a relatively softer pad. and conditioning, relatively constant times can be used for polishing the dissimilar materials (56, 58). This makes polishing more predictable and increases the number of substrates that can be polished using a single polishing pad (34). Polishing pads (34) are typically changed when other maintenance is performed on the polisher rather than when the polishing rate becomes too low.

Abstract: A chemical mechanical polishing (CMP) method utilizes a polishing pad (21) and an under pad (20). The under pad (20) has an edge portion (24) and a central portion (22). The central portion (22) has either a shore D hardness less than a shore D hardness of the portion (24), greater slurry absorption than the edge portion (24), or more compressibility than the edge portion (24). This composite material under pad (20) will improve polishing uniformity of a semiconductor wafer (39). In addition, the use of the polishing pads (20 and 21) allows for greater final wafer profile control than was previously available in the art (FIGS. 4-6).

Abstract: The present invention provides cis-epoxide compounds represented by formula (I-1), (I-2) or (I-3) which are useful for treating or preventing diseases caused by HIV infection: ##STR1## wherein: A, B, D, E, R.sup.1, R.sup.10, R.sup.11, K, G, Q, r and J have the meanings as defined in the specification.

Abstract: A method of sputtering material onto semiconductor wafers includes: a) providing a sputtering chamber with a sputtering target, a wafer supporting chuck having a supported first wafer, and a collimator positioned between the target and first wafer for filtering material sputtered from the target onto the first wafer; b) providing ionized sputtering atoms within the chamber; c) bombarding the target with the ionized sputtering atoms to dislodge target atoms; d) passing the dislodged target atoms through collimator openings and onto the first wafer, the dislodged target atoms coating the collimator and openings passing therethrough; e) removing the sputter deposited first wafer from the sputtering chamber without breaking vacuum; f) after removing the sputtered first wafer, cleaning the collimator within the chamber without breaking vacuum between removal of the first wafer and the cleaning of the collimator within the chamber; and g) after cleaning of the collimator within the chamber, providing a second wafer

Abstract: Methods of hyperfine patterning and manufacturing semiconductor devices. Steps in accordance with the present invention include coating a hemisphere particle layer having hills and valleys on a layer to be etched, the hemisphere particle layer having an etch selectivity higher than that of the first layer, filling the valleys of the hemisphere particle layer with a second layer having an etch selectivity higher than that of the hemisphere particle layer, and etching back the hills of the hemisphere particle layer to expose the first layer by using the second layer as a mask, and etching the first layer. By virtue of the hemisphere particle layer having alternating hills and valleys, it is possible to accomplish a hyperfine patterning of about 0.1 .mu.m. Since the mean size and the density of hills and valleys of the hemisphere layer can be controlled, the pattern size also can be controlled.

Abstract: In semiconductor manufacture a method of shaping the features of a semiconductor structure using chemical mechanical planarization (CMP) is provided. During CMP, a relatively soft polishing pad is utilized to conform to and contour a topography of the semiconductor structure. Another layer of a material such as a dielectric (e.g. TEOS based silicon dioxide) can then be deposited over the contoured topography without the inclusion of voids. The method of the invention is particularly suited to the formation of void free dielectric layers.

Abstract: A process for depositing a thin film of aluminum nitride (AlN) includes sputtering an aluminum target with energetic nitrogen ions generated in a nitrogen plasma. A single gas (i.e. nitrogen) is used as both the reactive gas and as the sputtering gas. The process is especially adapted for forming an etchstop layer for use in forming contact vias through a dielectric layer in semiconductor manufacture. The process is also useful in semiconductor manufacture for forming an aluminum nitride (AlN) film that may be used as a passivation layer, as a ceramic packaging material, as a mask for ion implantation, as a substrate material in hybrid circuits, and as a high bandgap window for GaAs solar cells.

Abstract: Methods of hyperfine patterning and manufacturing semiconductor devices. Steps in accordance with the present invention include coating a hemisphere particle layer having hills and valleys on a layer to be etched, the hemisphere particle layer having an etch selectivity higher than that of the first layer, filling the valleys of the hemisphere particle layer with a second layer having an etch selectivity higher than that of the hemisphere particle layer, and etching back the hills of the hemisphere particle layer to expose the first layer by using the second layer as a mask, and etching the first layer. By virtue of the hemisphere particle layer having alternating hills and valleys, it is possible to accomplish a hyperfine patterning of about 0.1 .mu.m. Since the mean size and the density of hills and valleys of the hemisphere layer can be controlled, the pattern size also can be controlled.

Abstract: A barrier material for use in preventing interdiffusion of silicon and aluminum at silicon/aluminum interfaces comprises a layer of titanium, aluminum, and nitrogen between about 100.ANG. and 1000.ANG. thick. The barrier material comprises between 1% and 20% aluminum, between 30% and 60% titanium, and between 30% and 60% nitrogen. The TiAlN material is more resistant to diffusion than TiN and can be etched and sputtered like TiN. It has better thermal budget than TiN and better stability on silicon, and thus can replace TiN in many of its uses in semiconductor devices.

Abstract: A heat exchanger utilizes a double walled heat transfer tube wherein the inner tube has a knurled external surface engaging the inner surface of an outer tube to provide multiple interconnected leak paths. The inner and outer tubes are attached to inner and outer tube sheets by roller expansion.

Abstract: A double-walled finned heat transfer tube is provided for use in heat exchangers. The heat transfer tube includes an inner tube inserted within an externally finned outer tube. The assembly is subjected to a crimping operation which produces radial convexities along the length of the outer tube which serve to lock the inner tube and outer tube together in intimate heat conducting relationship and which produces radial concavities between the inner and outer tubes which serve as leakage channels. The crimping operation also produces grooves in the external finned surface which improves heat transfer between the assembly and an external medium.

Abstract: A double-walled finned heat transfer tube is provided for use in heat exchangers. The heat transfer tube includes an inner tube inserted within an externally finned outer tube. The assembly is subjected to a crimping operation which produces radial convexities along the length of the outer tube which serve to lock the inner tube and outer tube together in intimate heat conducting relationship and which produces radial concavities between the inner and outer tubes which serve as leakage channels. The crimping operation also produces grooves in the external finned surface which improves heat transfer between the assembly and an external medium.