Abstract: A method of manufacturing a solder bump structure on a semiconductor device is provided. In one embodiment, a semiconductor substrate is provided having a bonding pad and a passivation layer formed thereabove, the passivation layer having an opening therein exposing a portion of the bonding pad. A first under bump metallization (UBM) layer is formed over the bonding pad and the passivation layer. A mask layer is placed over the first UBM layer, the mask layer having an opening therein exposing a portion of the first UBM layer. The mask layer is thereafter etched to create a recess at the edges between the first UBM layer and the mask layer. A second UBM layer is deposited in the opening of the mask layer, the second UBM layer filling the recess and a portion of the opening of the mask layer.

Abstract: A method of manufacturing a solder bump structure on a semiconductor device is provided. In one embodiment, a semiconductor substrate is provided having a bonding pad and a passivation layer formed thereabove, the passivation layer having an opening therein exposing a portion of the bonding pad. A first under bump metallization (UBM) layer is formed over the bonding pad and the passivation layer. A mask layer is placed over the first UBM layer, the mask layer having an opening therein exposing a portion of the first UBM layer. The mask layer is thereafter etched to create a recess at the edges between the first UBM layer and the mask layer. A second UBM layer is deposited in the opening of the mask layer, the second UBM layer filling the recess and a portion of the opening of the mask layer.

Abstract: Methods for forming a bump on a semiconductor substrate, the substrate having a contact pad thereon, is provided. In one embodiment, the method comprises depositing a passivation layer over the substrate and the contact pad. The passivation layer is patterned and etched to form a plurality of openings in the passivation layer exposing portions of the contact pad. An under bump metallurgy (UBM) layer is deposited over the etched passivation layer and in the plurality of openings thereof to contact the contact pad. A photoresist layer is formed on the UBM layer and then patterned and etched to form at least one opening substantially overlying the contact pad. An electrically conductive material is deposited into the opening formed in the photoresist layer and overlying the UBM layer and aligned with the contact pad. A portion of the remaining photoresist layer is removed. The UBM layer is etched using the electrically conductive material as a mask.

Abstract: Methods for forming a bump on a semiconductor substrate, the substrate having a contact pad thereon, is provided. In one embodiment, the method comprises depositing a passivation layer over the substrate and the contact pad. The passivation layer is patterned and etched to form a plurality of openings in the passivation layer exposing portions of the contact pad. An under bump metallurgy (UBM) layer is deposited over the etched passivation layer and in the plurality of openings thereof to contact the contact pad. A photoresist layer is formed on the UBM layer and then patterned and etched to form at least one opening substantially overlying the contact pad. An electrically conductive material is deposited into the opening formed in the photoresist layer and overlying the UBM layer and aligned with the contact pad. A portion of the remaining photoresist layer is removed. The UBM layer is etched using the electrically conductive material as a mask.

Abstract: A method for developing a photo-exposed photoresist layer to improve a critical dimension uniformity (CDU) for a semiconductor device manufacturing process including providing a semiconductor process wafer having a process surface comprising a photoresist layer photo-exposed according to an exposure pattern; dispensing a predetermined amount of developer solution over a stationary semiconductor process wafer to form a film of developer solution covering the process surface; partially developing the exposed portions of the photoresist layer comprising maintaining the semiconductor process wafer in a stationary position for a predetermined time period; rotating the semiconductor process wafer for a predetermined period of time to remove a portion of the developer solution; and, repeating the steps of dispensing, partially developing, and rotating, for a predetermined number of repetition cycles to complete a photoresist development process.

Abstract: A method for developing a photo-exposed photoresist layer to improve a critical dimension uniformity (CDU) for a semiconductor device manufacturing process including providing a semiconductor process wafer having a process surface comprising a photoresist layer photo-exposed according to an exposure pattern; dispensing a predetermined amount of developer solution over a stationary semiconductor process wafer to form a film of developer solution covering the process surface; partially developing the exposed portions of the photoresist layer comprising maintaining the semiconductor process wafer in a stationary position for a predetermined time period; rotating the semiconductor process wafer for a predetermined period of time to remove a portion of the developer solution; and, repeating the steps of dispensing, partially developing, and rotating, for a predetermined number of repetition cycles to complete a photoresist development process.