Abstract: The present disclosure relates to a method of preparing a polymer, which includes: adding an alkyl-substituted aromatic vinyl-based monomer and a vinyl cyanide-based monomer to a reactor and initiating polymerization; and performing polymerization while continuously adding an alkyl-substituted aromatic vinyl-based monomer and a multifunctional initiator to the reactor, wherein the continuous addition of the alkyl-substituted aromatic vinyl-based monomer and the multifunctional initiator is initiated when a polymerization conversion rate is 10 to 30%, and the continuous addition of the alkyl-substituted aromatic vinyl-based monomer and the multifunctional initiator is terminated when a polymerization conversion rate is 70 to 80%.

Abstract: The present disclosure relates to a method of preparing an organic zinc catalyst through solid phase blending that does not require a solvent and a washing process, and a method of preparing a polyalkylene carbonate resin by using the organic zinc catalyst prepared thereby.

Abstract: The present invention provides an organic compound represented by: an organic light emitting diode and an organic light emitting display device using the organic compound. The organic compound of the present invention is capable of reducing a driving voltage of an organic light emitting diode and improving an emitting efficiency and a lifetime of the organic light emitting diode and the organic light emitting display device including the organic compound.

Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.

Abstract: Example embodiments are directed to a delay locked loop (DLL) circuit based on a hybrid finite impulse response (FIR) filtering technique, and a semiconductor memory device including the DLL circuit. The DLL circuit includes a frequency divider and a self-referenced multiphase generator (SRMG) and allows a Sigma-Delta (??) modulator to operate at a low frequency without generating false lock and glitch noise.

Abstract: Example embodiments are directed to a delay locked loop (DLL) circuit based on a hybrid finite impulse response (FIR) filtering technique, and a semiconductor memory device including the DLL circuit. The DLL circuit includes a frequency divider and a self-referenced multiphase generator (SRMG) and allows a Sigma-Delta (??) modulator to operate at a low frequency without generating false lock and glitch noise.

Abstract: A phase frequency detector for improving in-band phase noise characteristics of a PLL is disclosed. The phase frequency detector compares a reference frequency with a division frequency created by dividing an output frequency of a voltage controlled oscillator (VCO) by a predetermined division ratio, creates a phase-difference signal corresponding to a phase difference between the reference frequency and the division frequency, and improves noise characteristics.

Abstract: The invention relates to method of determining a fractional division ratio using a sigma-delta modulator. In this method, the fractional division ratio of the sigma-delta modulator is set as k/q, where k is an integer input value of the sigma-delta modulator, and q is a value preset to determine a predetermined frequency resolution. A spur generated from the voltage controller oscillator according to the variation of k is measured while the value k is varied. When the spur takes place at a certain value of k where a frequency is lower than a predetermined reference frequency, the fractional division ratio is reset as k/(q+1) or k/(q?1) for the certain value of k. The reset fractional division ratio is provided to the divider.

Abstract: The invention provides a low divide ratio programmable frequency divider of a fractional-N type applied to a digital MOPLL tuner and a method thereof. In the invention, a divide ratio assigner assigns divide data as a main divide ratio and a pulse swallow value according to a first or a second dividing operation mode in response to a mode selection signal. A prescaler operates on the first or second divide operation mode in response to the mode selection signal. Also, a main counter divides a frequency from the prescaler by the main divide ratio. Further, a pulse swallow counter counts a clock of the main counter while outputting a pulse swallow signal to the prescaler. The pulse swallow signal has a swallow level if a counting value corresponds to the pulse swallow value, and a non-swallow level if the counting value does not correspond to the pulse swallow value.

Abstract: A phase frequency detector for improving in-band phase noise characteristics of a PLL is disclosed. The phase frequency detector compares a reference frequency with a division frequency created by dividing an output frequency of a voltage controlled oscillator (VCO) by a predetermined division ratio, creates a phase-difference signal corresponding to a phase difference between the reference frequency and the division frequency, and improves noise characteristics.