Abstract: A modem chip includes a processor configured to generate instructions, a timing controller configured to respectively generate control signals corresponding to the instructions at the execution times of the instructions, and a plurality of intellectual property blocks, each configured to operate in response to a corresponding control signal of the control signals. The timing controller includes a heap sorting circuit configured to sort the instructions according to execution orders of the instructions based on heap sorting using the execution times, a reference counter configured to generate a reference time, and a signal generator configured to generate a control signal corresponding to a current instruction when the reference time matches the execution time of the current instruction having a highest execution order among the instructions.

Abstract: A modem chip includes a processor configured to generate instructions, a timing controller configured to respectively generate control signals corresponding to the instructions at the execution times of the instructions, and a plurality of intellectual property blocks, each configured to operate in response to a corresponding control signal of the control signals. The timing controller includes a heap sorting circuit configured to sort the instructions according to execution orders of the instructions based on heap sorting using the execution times, a reference counter configured to generate a reference time, and a signal generator configured to generate a control signal corresponding to a current instruction when the reference time matches the execution time of the current instruction having a highest execution order among the instructions.

Abstract: A storage device, method for processing a plurality of pieces of client data, and a chipset are provided. The storage device includes a first stage storage unit configured to receive the plurality of pieces of client data generated in bursts from a plurality of clients and store the received plurality of pieces of client data; a second stage storage unit configured to receive the plurality of pieces of client data from the first stage storage unit and store the received plurality of pieces of client data in a plurality of memory banks shared by the plurality of clients, respectively, in bursts; and a third stage storage unit configured to receive each of the plurality of pieces of client data from the second stage storage unit and store data of a transaction unit corresponding to a transmission unit for data processing.

Abstract: A storage device, method for processing a plurality of pieces of client data, and a chipset are provided. The storage device includes a first stage storage unit configured to receive the plurality of pieces of client data generated in bursts from a plurality of clients and store the received plurality of pieces of client data; a second stage storage unit configured to receive the plurality of pieces of client data from the first stage storage unit and store the received plurality of pieces of client data in a plurality of memory banks shared by the plurality of clients, respectively, in bursts; and a third stage storage unit configured to receive each of the plurality of pieces of client data from the second stage storage unit and store data of a transaction unit corresponding to a transmission unit for data processing.

Abstract: An automatic gain control apparatus and method for a compressed mode in a MIMO system are provided. The method includes determining power at a first frequency band using a first receiver, simultaneously determining power at a second frequency band using a second receiver in a compressed mode, if the second receiver changes a power determination frequency band into the first frequency band, correcting the power determination value of the first receiver, and applying the corrected power determination value of the first receiver to the second receiver.

Abstract: An apparatus and method for measuring a Signal-to-Interference-plus-Noise Ratio (SINR) by controlling a residual gain in a high speed packet access system are provided. The apparatus includes a gain controller for measuring an intensity of a signal outputted from a residual gain controller, for outputting a gain control signal for controlling a gain of an interval of a preset gain resolution of a radio frequency integrated circuit according to the intensity of measured signal, and for outputting a residual gain value for controlling a residual gain less than the preset gain resolution, wherein the radio frequency integrated circuit gain-controls a signal inputted according to the gain control signal, and the residual gain controller multiplies the gain-controlled signal by the residual gain value to compensate the residual gain.

Abstract: An apparatus and method for measuring a Signal-to-Interference-plus-Noise Ratio (SINR) by controlling a residual gain in a high speed packet access system are provided. The apparatus includes a gain controller for measuring an intensity of a signal outputted from a residual gain controller, for outputting a gain control signal for controlling a gain of an interval of a preset gain resolution of a radio frequency integrated circuit according to the intensity of measured signal, and for outputting a residual gain value for controlling a residual gain less than the preset gain resolution, wherein the radio frequency integrated circuit gain-controls a signal inputted according to the gain control signal, and the residual gain controller multiplies the gain-controlled signal by the residual gain value to compensate the residual gain.

Abstract: An automatic gain control apparatus and method for a compressed mode in a MIMO system are provided. The method includes determining power at a first frequency band using a first receiver, simultaneously determining power at a second frequency band using a second receiver in a compressed mode, if the second receiver changes a power determination frequency band into the first frequency band, correcting the power determination value of the first receiver, and applying the corrected power determination value of the first receiver to the second receiver.

Abstract: An apparatus and method for generating reference timings. Each of at least two Node Bs transmits a first channel signal for providing a reference timing and a second channel signal different from the first channel signal and a UE has a plurality of fingers for demodulating the first channel signals. A first timing generator receives an SFN of a reference Node B having a communication link established with the UE, selects a first channel FB timing from a reference finger, and generates an SFN reference timing based on the SFN and the selected first channel FB timing. A second timing generator generates a second channel FB timing to demodulate the second channel signal of the reference Node B from the selected first channel FB timing through offset control. A third timing generator generates an uplink channel FB timing having a predetermined offset from the second channel FB timing.

Abstract: An interleaver is disclosed for a turbo encoder in an UMTS. The interleaver includes a register for updating and registering a plurality of parameters for setting an operating condition of the interleaver; a controller for generating a control signal for controlling an operation of the system by receiving the operating condition from the register; an address calculator for generating a finally interleaved address using an inter-row permutation pattern T(j), an intra-row permutation pattern increment arrangement value incr(j) and an intra-row permutation basic sequence s(i), provided from the register according to the control signal generated by the controller; and a data storage for sequentially storing data input to the turbo encoder and outputting data corresponding to the address generated by the address calculator.

Abstract: A rake receiver for high data rate communications systems is provided that is able to share resources between demodulating branches without using independent hardware resources for each finger. The rake receiver of the present invention uses less circuitry while keeping functional equivalence, and it requires relatively smaller additional area when increasing the number of demodulating branches, thereby having a significantly smaller size, being able to track more demodulating paths for increasing performance, and being less complex as compared to conventional rake receivers for high data rate communications systems.

Abstract: A symbol combining device for multi-path diversity includes a plurality of demodulation circuits for demodulating received signals, a common memory for storing outputs of the demodulation circuits, a symbol combiner for receiving the outputs of the common memory corresponding to the demodulation circuits and for combining the outputs, and a memory controller for controlling the common memory to timely separate the write and read operations. To timely separate the write and read operations, the memory controller controls the common memory in order that the demodulation circuits sequentially access the common memory and the resultant outputs of the demodulation circuits are written in the common memory, and the symbol combiner reads the outputs of the demodulation circuits written in the common memory sequentially.

Abstract: An apparatus and method for generating reference timings. Each of at least two Node Bs transmits a first channel signal for providing a reference timing and a second channel signal different from the first channel signal and a UE has a plurality of fingers for demodulating the first channel signals. A first timing generator receives an SFN of a reference Node B having a communication link established with the UE, selects a first channel FB timing from a reference finger, and generates an SFN reference timing based on the SFN and the selected first channel FB timing. A second timing generator generates a second channel FB timing to demodulate the second channel signal of the reference Node B from the selected first channel FB timing through offset control. A third timing generator generates an uplink channel FB timing having a predetermined offset from the second channel FB timing.

Abstract: A rake receiver for high data rate communications systems is provided that is able to share resources between demodulating branches without using independent hardware resources for each finger. The rake receiver of the present invention uses less circuitry while keeping functional equivalence, and it requires relatively smaller additional area when increasing the number of demodulating branches, thereby having a significantly smaller size, being able to track more demodulating paths for increasing performance, and being less complex as compared to conventional rake receivers for high data rate communications systems.

Abstract: A symbol combining device for multi-path diversity includes a plurality of demodulation circuits for demodulating received signals, a common memory for storing outputs of the demodulation circuits, a symbol combiner for receiving the outputs of the common memory corresponding to the demodulation circuits and for combining the outputs, and a memory controller for controlling the common memory to timely separate the write and read operations. To timely separate the write and read operations, the memory controller controls the common memory in order that the demodulation circuits sequentially access the common memory and the resultant outputs of the demodulation circuits are written in the common memory, and the symbol combiner reads the outputs of the demodulation circuits written in the common memory sequentially.

Abstract: An interleaver is disclosed for a turbo encoder in an UMTS. The interleaver includes a register for updating and registering a plurality of parameters for setting an operating condition of the interleaver; a controller for generating a control signal for controlling an operation of the system by receiving the operating condition from the register; an address calculator for generating a finally interleaved address using an inter-row permutation pattern T(j), an intra-row permutation pattern increment arrangement value incr(j) and an intra-row permutation basic sequence s(i), provided from the register according to the control signal generated by the controller; and a data storage for sequentially storing data input to the turbo encoder and outputting data corresponding to the address generated by the address calculator.