Patents by Inventor Sung Eom
Sung Eom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923406Abstract: A semiconductor device includes: a first insulating layer, a plurality of first electrodes penetrating the first insulating layer, a plurality of second electrodes penetrating the first insulating layer, the plurality of second electrodes being located between the plurality of first electrodes: a first high dielectric constant layer having a dielectric constant higher than a dielectric constant of the first insulating layer, a plurality of third electrodes penetrating the first high dielectric constant layer, the plurality of third electrodes being respectively connected to the plurality of first electrodes, and a plurality of fourth electrodes penetrating the first high dielectric constant layer, the plurality of fourth electrodes being located between the plurality of third electrodes.Type: GrantFiled: September 3, 2021Date of Patent: March 5, 2024Assignee: SK hynix Inc.Inventor: Dae Sung Eom
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Publication number: 20240021570Abstract: Provided is a bonding apparatus. The bonding apparatus includes a stage configured to accommodate a substrate, a laser light source configured to provide laser light to devices on the substrate, and a bonding plate provided between the laser light source and the stage and configured to provide the devices on the substrate. The bonding plate includes a transparent substrate; a transparent layer below the transparent substrate; an device adhesion layer below the transparent layer and a reflective pattern provided above or below the transparent substrate and the transparent layer.Type: ApplicationFiled: July 5, 2023Publication date: January 18, 2024Inventors: Jiho JOO, Yong Sung EOM, CHANMI LEE, Ki Seok JANG, GWANG-MUN CHOI, KWANG-SEONG CHOI, Jin Hyuk OH
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Publication number: 20240015966Abstract: A semiconductor memory device includes a gate stack structure including a plurality of conductive layers stacked to be spaced apart from each other in a first direction, the gate stack structure surrounding the periphery of a polygonal opening. The semiconductor memory device also includes a stepped structure formed along a sidewall of the polygonal opening.Type: ApplicationFiled: December 14, 2022Publication date: January 11, 2024Applicant: SK hynix Inc.Inventor: Dae Sung EOM
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Publication number: 20240008272Abstract: A semiconductor device includes: a stacked structure comprising a plurality of dielectric layers and a plurality of conductive layers, wherein the dielectric layers are alternately stacked with the conductive layers; a groove formed for each conductive layer by recessing the conductive layer to the inside of the stacked structure; and an isolation structure formed through the stacked structure so as to isolate the stacked structure into a first block and a second block. The isolation structure comprises a first isolation structure and a second isolation structure adjacent to the first isolation structure with a gap provided between the first and second isolation structures, and one end of the first isolation structure and the other end of the second isolation structure, which face each other, have a vortex shape when viewed from above.Type: ApplicationFiled: September 15, 2023Publication date: January 4, 2024Applicant: SK hynix Inc.Inventor: Dae Sung EOM
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Publication number: 20230391956Abstract: Provided is an organic-inorganic compound including a first structural body and a curable reactive group, wherein the first structural body may have a structure in which silane and isohexide are chemically bonded through a silyl ether bond.Type: ApplicationFiled: June 2, 2023Publication date: December 7, 2023Inventors: GWANG-MUN CHOI, Yong Sung EOM, Jiho JOO, KWANG-SEONG CHOI, Seok-Hwan MOON, Jin Hyuk OH, Ho-Gyeong YUN, CHANMI LEE, Ki Seok JANG
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Publication number: 20230326810Abstract: Provided are a microwave heating device and a method for manufacturing a semiconductor packaging using the same. The microwave heating device includes a microwave generator configured to generate microwaves, a microwave absorbing layer configured to receive the microwaves so as to be heated, a temperature measuring layer provided on the microwave absorbing layer, a sensor configured to detect a temperature of the temperature measuring layer, and a controller connected to the sensor and the microwave generator to determine the temperature of the microwave absorbing layer using a detection signal of the sensor, the controller being configured to control a voltage of the microwaves provided from the microwave generator based on the temperature of the microwave absorbing layer.Type: ApplicationFiled: April 7, 2023Publication date: October 12, 2023Applicant: Electronics and Telecommunications Research InstituteInventors: GWANG-MUN CHOI, Yong Sung EOM, Jiho JOO, KWANG-SEONG CHOI, Seok-Hwan MOON, Jin Hyuk OH, Ho-Gyeong YUN, CHANMI LEE, Ki Seok JANG
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Patent number: 11765895Abstract: A semiconductor device includes: a stacked structure comprising a plurality of dielectric layers and a plurality of conductive layers, wherein the dielectric layers are alternately stacked with the conductive layers; a groove formed for each conductive layer by recessing the conductive layer to the inside of the stacked structure; and an isolation structure formed through the stacked structure so as to isolate the stacked structure into a first block and a second block. The isolation structure comprises a first isolation structure and a second isolation structure adjacent to the first isolation structure with a gap provided between the first and second isolation structures, and one end of the first isolation structure and the other end of the second isolation structure, which face each other, have a vortex shape when viewed from above.Type: GrantFiled: July 28, 2022Date of Patent: September 19, 2023Assignee: SK hynix Inc.Inventor: Dae Sung Eom
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Publication number: 20230217651Abstract: A semiconductor memory device includes: a semiconductor substrate including a first region and a second region; a memory cell array over the first region of the semiconductor substrate; a dummy stack structure over the second region of the semiconductor substrate; a chip guard structure penetrating the dummy stack structure; and a void-containing structure penetrating the dummy stack structure.Type: ApplicationFiled: June 9, 2022Publication date: July 6, 2023Applicant: SK hynix Inc.Inventor: Dae Sung EOM
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Patent number: 11677060Abstract: Provided is a method for transferring and bonding devices. The method includes applying an adhesive layer to a carrier, arranging a plurality of devices, attaching the arranged devices to the carrier, applying a polymer film to a substrate, aligning the carrier to which the plurality of devices are attached with the substrate, bonding the plurality of devices to the substrate by radiating laser, and releasing the carrier from the substrate to which the plurality of devices are bonded.Type: GrantFiled: April 12, 2021Date of Patent: June 13, 2023Assignee: ELECTRONICS AND TELEOCMMUNICATIONS RESEARCH INSTITUTEInventors: Jiho Joo, Yong Sung Eom, Gwang-Mun Choi, Kwang-Seong Choi, Chanmi Lee, Ki Seok Jang
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Patent number: 11618109Abstract: Provided is a wire for electric bonding, which includes a solder wire and a composition for bonding adjacent to the solder wire, the solder wire is wet when reaches to a melting point as heat is transferred, the composition for bonding includes an epoxy resin, a reducing agent, and a curing agent, the reducing agent removes a metal oxide formed on a surface of the solder wire, and the epoxy resin is cured by chemically reacting with the reducing agent and the curing agent at a curing temperature.Type: GrantFiled: June 30, 2021Date of Patent: April 4, 2023Assignee: Electronics and Telecommunications Research InstituteInventors: Gwang-Mun Choi, Yong Sung Eom, Kwang-Seong Choi, Jiho Joo, Chanmi Lee, Ki Seok Jang
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Publication number: 20230027892Abstract: Provided is an electronic device including a plurality of substrate electrodes on a substrate, the substrate electrodes including initial electrodes and spare electrodes, a bonding material covering the initial electrodes and the spare electrodes, module structures respectively provided on first initial electrodes of the initial electrodes, and solders between each of the first initial electrodes and each of the module structures, wherein the spare electrodes include second spare electrodes, wherein the module structures are not provided on the second spare electrodes, wherein the bonding material on the first initial electrodes is harder than the bonding material on the second spare electrodes.Type: ApplicationFiled: July 14, 2022Publication date: January 26, 2023Applicant: Electronics and Telecommunications Research InstituteInventors: KWANG-SEONG CHOI, Yong-Sung EOM, Jiho JOO, GWANG-MUN CHOI, Seok-Hwan MOON, Ho-Gyeong YUN, CHANMI LEE, Ki-Seok JANG
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Publication number: 20220402070Abstract: Provided are a laser control structure and a laser bonding method using the same, and more particularly, a laser bonding method including: forming bonding portions on a substrate; providing a bonding object onto the bonding portions; providing a laser control structure onto the bonding object or the substrate; irradiating a laser toward the bonding object and the bonding portions; controlling quantity of laser light absorbed through the laser control structure; using the controlled quantity of laser light to heat the bonding portions and the bonding object to a bonding temperature; and bonding the bonding portions and the bonding object, wherein the laser control structure includes: a first substrate including a first region and a second region; a first thin film laminate on the first region; and a second thin film laminate on the second region, wherein: the first thin film laminate includes at least one first thin film layer and at least one second thin film layer, which are laminated on the first region; thType: ApplicationFiled: June 17, 2022Publication date: December 22, 2022Applicant: Electronics and Telecommunications Research InstituteInventors: Ki Seok JANG, Yong Sung EOM, GWANG-MUN CHOI, KWANG-SEONG CHOI, Jiho JOO, Seok-Hwan MOON, CHANMI LEE
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Publication number: 20220384674Abstract: Provided is a method for manufacturing an electronic device. The method for manufacturing the electronic device includes mapping good elements and defective elements on a substrate, providing a first transparent structure including a first adhesive layer on the substrate, selectively providing first laser light to the defective elements to cure the first adhesive layer on the defective elements and separate the defective elements from the substrate, providing a second transparent structure including a second adhesive layer, which adheres to new elements replaced for the defective elements, on the substrate, and selectively providing second laser light to the new elements to bond the new elements to the substrate.Type: ApplicationFiled: May 31, 2022Publication date: December 1, 2022Inventors: Jiho JOO, Yong Sung EOM, Kwang-Seong CHOI, Chanmi LEE, Gwang-Mun CHOI, Ki Seok JANG, Seok-Hwan MOON, Ho-Gyeong YUN
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Publication number: 20220367502Abstract: A semiconductor device includes: a stacked structure comprising a plurality of dielectric layers and a plurality of conductive layers, wherein the dielectric layers are alternately stacked with the conductive layers; a groove formed for each conductive layer by recessing the conductive layer to the inside of the stacked structure; and an isolation structure formed through the stacked structure so as to isolate the stacked structure into a first block and a second block. The isolation structure comprises a first isolation structure and a second isolation structure adjacent to the first isolation structure with a gap provided between the first and second isolation structures, and one end of the first isolation structure and the other end of the second isolation structure, which face each other, have a vortex shape when viewed from above.Type: ApplicationFiled: July 28, 2022Publication date: November 17, 2022Applicant: SK hynix Inc.Inventor: Dae Sung EOM
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Patent number: 11488841Abstract: Provided is a method for manufacturing a semiconductor package, the method including providing a semiconductor chip on a substrate, providing a bonding member between the substrate and the semiconductor chip, and bonding the semiconductor chip on the substrate by irradiating of a laser on the substrate. Here, the bonding member may include a thermosetting resin, a curing agent, and a laser absorbing agent.Type: GrantFiled: February 19, 2020Date of Patent: November 1, 2022Assignee: Electronics and Telecommunications Research InstituteInventors: Yong Sung Eom, Kwang-Seong Choi, Ki Seok Jang, Seok-Hwan Moon, Jiho Joo
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Publication number: 20220302248Abstract: A semiconductor device includes: a first insulating layer, a plurality of first electrodes penetrating the first insulating layer, a plurality of second electrodes penetrating the first insulating layer, the plurality of second electrodes being located between the plurality of first electrodes: a first high dielectric constant layer having a dielectric constant higher than a dielectric constant of the first insulating layer, a plurality of third electrodes penetrating the first high dielectric constant layer, the plurality of third electrodes being respectively connected to the plurality of first electrodes, and a plurality of fourth electrodes penetrating the first high dielectric constant layer, the plurality of fourth electrodes being located between the plurality of third electrodes.Type: ApplicationFiled: September 3, 2021Publication date: September 22, 2022Applicant: SK hynix Inc.Inventor: Dae Sung EOM
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Patent number: 11404428Abstract: A semiconductor device includes: a stacked structure comprising a plurality of dielectric layers and a plurality of conductive layers, wherein the dielectric layers are alternately stacked with the conductive layers; a groove formed for each conductive layer by recessing the conductive layer to the inside of the stacked structure; and an isolation structure formed through the stacked structure so as to isolate the stacked structure into a first block and a second block. The isolation structure comprises a first isolation structure and a second isolation structure adjacent to the first isolation structure with a gap provided between the first and second isolation structures, and one end of the first isolation structure and the other end of the second isolation structure, which face each other, have a vortex shape when viewed from above.Type: GrantFiled: July 2, 2020Date of Patent: August 2, 2022Assignee: SK hynix Inc.Inventor: Dae Sung Eom
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Publication number: 20220173029Abstract: A semiconductor device includes a first conductive pattern having a first line portion extending in a first direction and a first bending portion that extends from the first line portion. A closed area, surrounded by the first line portion and the first bending portion, is defined at one side of the first line portion. The semiconductor device further includes a second conductive pattern disposed in the closed area, the second conductive pattern being spaced apart from the first conductive pattern.Type: ApplicationFiled: February 16, 2022Publication date: June 2, 2022Applicant: SK hynix Inc.Inventor: Dae Sung EOM
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Publication number: 20220102603Abstract: Provided is a method of fabricating a semiconductor package. The method of fabricating the semiconductor package include preparing a lower element including a lower substrate, a lower electrode, an UBM layer, and a reducing agent layer, providing an upper element including an upper substrate, an upper electrode, and a solder bump layer, providing a pressing member on the upper substrate to press the upper substrate to the lower substrate, and providing a laser beam passing through the pressing member to bond the upper element to the lower element.Type: ApplicationFiled: August 11, 2021Publication date: March 31, 2022Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Kwang-Seong CHOI, Yong Sung EOM, Jiho JOO, Gwang-Mun CHOI, Seok-Hwan MOON, Chanmi LEE, Ki Seok JANG
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Patent number: 11289420Abstract: A semiconductor device includes a first conductive pattern having a first line portion extending in a first direction and a first bending portion that extends from the first line portion. A closed area, surrounded by the first line portion and the first bending portion, is defined at one side of the first line portion. The semiconductor device further includes a second conductive pattern disposed in the closed area, the second conductive pattern being spaced apart from the first conductive pattern.Type: GrantFiled: June 12, 2019Date of Patent: March 29, 2022Assignee: SK hynix Inc.Inventor: Dae Sung Eom